AD8197AASTZ-RL Analog Devices Inc, AD8197AASTZ-RL Datasheet - Page 22

• Manufacturer Part Number: AD8197AASTZ-RL
• Description: IC,Telecom Switching Circuit,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8197AASTZ-RL

• Function: Switch
• Circuit: 1 x 4:1
• On-state Resistance: 50 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8197A
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channel Enable Bit
Table 19. PP_EN Description
PP_EN
0
1
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 20. High Speed Switch Mapping
PP_CH[1:0]
00
01
10
11
AUXILIARY DEVICE MODES REGISTER
The auxiliary (low speed) switch is always enabled when using
the parallel interface.
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mapping
PP_CH[1:0]
00
01
10
11
RECEIVER SETTINGS REGISTER
High speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
Description
High speed channels off, low power/standby mode
High speed channels on
O[3:0]
A[3:0]
B[3:0]
C[3:0]
D[3:0]
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]0
AUX_C[3:0]
AUX_D[3:0]
High Speed Source A switched to
output
High Speed Source B switched to
output
High Speed Source C switched to
output
High Speed Source D switched to
output
Description
Description
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
Auxiliary Source C switched to
output
Auxiliary Source D switched to
output
Rev. 0 | Page 22 of 28
INPUT TERMINATION PULSE REGISTER 1 AND
REGISTER 2
High speed input (TMDS) channels pulse-on-source switching
fixed to off when using the parallel interface.
RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2
PP_EQ: High Speed (TMDS) Input Equalization Level
Select Bit (For All TMDS Input Channels)
The input equalization cannot be set individually (per channel)
when using the parallel interface; one equalization setting
affects all input channels.
Table 22. PP_EQ Description
PP_EQ
0
1
TRANSMITTER SETTINGS REGISTER
PP_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (For All TMDS Channels)
Table 23. PP_PE[1:0] Description
PP_PE[1:0]
00
01
10
11
PP_OTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All TMDS Channels)
Table 24. PP_OTO Description
PP_OTO
0
1
PP_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All TMDS Channels)
Table 25. TX_OCL Description
PP_OCL
0
1
Description
Low equalization (6 dB)
High equalization (12 dB)
Description
Output current set to 10 mA
Output current set to 20 mA
Description
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
Description
Output termination off
Output termination on