AD8197 Analog Devices, AD8197 Datasheet
AD8197
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AD8197 Summary of contents
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... Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8197 to be configured as a 4:1 single HDMI/DVI link switch, a dual 8:1 switch single 16:1 switch. ...
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... AD8197 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Input Channels............................................................................ 13 Output Channels ........................................................................ 13 High Speed (TMDS) Switching Modes ................................... 14 Auxiliary Switch ...
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... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers PrA | Page AD8197 Min Typ Max Unit 2.25 Gbps −9 10 TBD ps (p-p) TBD ...
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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8197 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. ...
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... V 100-Lead LQFP 2.2 W AVCC − 1.4 V < V < IN MAXIMUM POWER DISSIPATION AVCC + 0.6 V The maximum power that can be safely dissipated by the AD8197 2 limited by the associated rise in junction temperature. The DVEE − 0.3 V < V < IN AMUXVCC + 0.6 V maximum safe junction temperature for plastic encapsulated DVEE − 0.3 V < V < ...
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... AD8197 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic 1, 13, 22, 54, 63, 75 AVCC 2 IN_B0 3 IP_B0 4, 10, 16, 25, 51, 60, 66, 72 AVEE 5 IN_B1 6 IP_B1 7, 19, 57, 69 VTTI 8 IN_B2 9 IP_B2 11 IN_B3 12 IP_B3 14 IN_A0 15 IP_A0 Figure 3. Pin Configuration Type 1 Description Power Positive Analog Supply. 3.3 V nominal. ...
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... High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input. Control High Speed Output Enable Parallel Interface. Control High Speed Equalization Selection Parallel Interface. LS I/O Low Speed Input/Output. PrA | Page AD8197 ...
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... AD8197 Pin No. Mnemonic 79 AUX_D2 80 AUX_D1 81 AUX_D0 82 AMUXVCC 83 AUX_C3 84 AUX_C2 85 AUX_C1 86 AUX_C0 87 AUX_COM3 88 AUX_COM2 89 AUX_COM1 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 Type Description LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. ...
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... Figure 6. RX Eye Diagram at TP2 (Cable = 20 meters, 24 AWG) Figure 4. Test Circuit Diagram for RX Eye Diagram Figure 7. RX Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 8. RX Eye Diagram at TP3 (Cable = 20 meters, 24 AWG) PrA | Page AD8197 7 − 1, data rate = 2.25 Gbps, unless ...
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... AD8197 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted. Figure 10. TX Eye Diagram at TP2 Figure 11. TX Eye Diagram at TP2 Figure 9 ...
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... Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup) Figure 15. Jitter vs. Data Rate Figure 16. Jitter vs. Supply Voltage 7 Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup) Figure 18. Eye Height vs. Data Rate Figure 19. Eye Height vs. Supply Voltage PrA | Page AD8197 − 1, data rate = 2.25 Gbps, unless ...
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... AD8197 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted. Figure 20. Jitter vs. Differential Input Swing Figure 21. Jitter vs. Temperature Figure 22. Rise and Fall Time vs. Temperature ...
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... AD8197 can be set without degrading the signal integrity, even for short input cables. At the 12 dB setting, the AD8197 can equalize more than 20 meters of 24 AWG cable at 2.25 Gbps. OUTPUT CHANNELS Each high speed output differential pair is terminated to the 3.3 V VTTO power supply through two 50 Ω ...
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... ONx mapping listed in Table 26. Dual Switching Mode In this mode, the AD8197 behaves as a locked dual [8:1] TMDS channel switch. The two 8:1 switches share the channel select input and, therefore, switch together. The user selects which two out of the eight possible input groups are routed to output by programming the HS_CH bits of the high speed device modes register in accordance with the switch mapping listed in Table 9 ...
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... Table 14. This mode is only accessible through the serial control interface. Single Switching Mode In this mode the AD8197 behaves as a single 16:1 TMDS channel multiplexer; a single channel, out of a possible 16, is routed to all of the outputs. The user selects which input channel is routed to the outputs by programming the AUX_CH bits of the auxiliary device modes register in accordance with the switch mapping listed in Table 15 ...
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... I2C_SDA line low). 2. Send the AD8197 part address (seven bits). The upper four bits of the AD8197 part address are the static value [1001] and the three LSBs are set by Input Pin I2C_ADDR2, Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This transfer should be MSB first ...
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... This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8197 to acknowledge the request. 11. The AD8197 serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Acknowledge the data from the AD8197. ...
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... PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 24. Following a reset, the AD8197 Preliminary Technical Data can be controlled through the parallel control interface until the first serial control event occurs ...
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... The serial interface configuration registers can be read and written using the I The least significant bits of the AD8197 I 3.3 V (Logic (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197 is reset as described in the Serial Control Interface section. ...
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... AD8197 Table 9. Dual Mode, 2× [8:1], High Speed Switch Mapping HS_CH[3:0] O[3:2] O[1:0] Description X000 A1 A0 The A0 and A1 high speed channels switched to output X001 A3 A2 The A2 and A3 high speed channels switched to output X010 B1 B0 The B0 and B1 high speed channels switched to output X011 B3 B2 The B2 and B3 high speed ...
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... The B2 and D2 auxiliary 1111 AUX_D3 channels switched to output The B3 and D3 auxiliary channels switched to output PrA | Page AD8197 Description Auxiliary Channel A0 switched to output Auxiliary Channel A1 switched to output Auxiliary Channel A2 switched to output Auxiliary Channel A3 switched to output Auxiliary Channel B0 switched to output Auxiliary Channel B1 ...
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... AD8197 RECEIVER SETTINGS REGISTER RX_TO: High Speed (TMDS) Channels Input Termination On/Off Select Bit Table 16. RX_TO Description RX_TO Description 0 Input termination off 1 Input termination on (can be pulsed on and off according to settings in the input termination pulse register) INPUT TERMINATION PULSE REGISTER 1 AND REGISTER 2 ...
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... PP_CH[1:0]: Auxiliary Switch Source Select Bus Table 27. Quad Auxiliary Switch Mode Mapping PP_CH[1: PrA | Page AD8197 Bit 1 Bit 0 High speed source select PP_CH[1] PP_CH[0] Auxiliary switch source select PP_CH[1] PP_CH[0] Input term. on/off ...
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... AD8197 RECEIVER SETTINGS REGISTER High speed (TMDS) channels input termination is fixed to on when using the parallel interface. INPUT TERMINATION PULSE REGISTER 1 AND REGISTER 2 High speed input (TMDS) channels pulse-on-source switching fixed to off when using the parallel interface. RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 ...
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... Preliminary Data Sheet APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197 Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197 is an HDMI/DVI switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1 ...
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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8197, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...
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... Ground Current Return In some applications, it can be necessary to invert the output pin order of the AD8197. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers necessary to also re- route the corresponding reference plane in order to provide one continuous ground current return path for the differential signals ...
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... AD8197 These four signals can be switched through the auxiliary bus of the AD8197 and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB ...
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... Figure 34. Figure 34. Recommended Pad Outline for Bypass Capacitors In applications where the AD8197 is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF capacitors ...
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... AD8197 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD8197ASTZ 1 −40°C to +85°C 1 AD8197ASTZ-RL −40°C to +85°C AD8197-EVAL Pb-free part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 25 0° 26 0.08 COPLANARITY VIEW A ...
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... Preliminary Data Sheet NOTES PrA | Page AD8197 ...
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... AD8197 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06471-0-12/06(PrA) Preliminary Technical Data PrA| Page ...