AD8197AASTZ-RL Analog Devices Inc, AD8197AASTZ-RL Datasheet
AD8197AASTZ-RL
Specifications of AD8197AASTZ-RL
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AD8197AASTZ-RL Summary of contents
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FEATURES 4 inputs, 1 output HDMI/DVI link Enables HDMI 1.3-compliant receiver Pin-to-pin compatible with the AD8191A 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for ...
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AD8197A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum ...
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SPECIFICATIONS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = differential input swing = 1000 mV, TMDS ...
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AD8197A Parameter 5 SERIAL CONTROL INTERFACE Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage PARALLEL CONTROL INTERFACE Input High Voltage Input Low Voltage ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating AVCC to AVEE 3.7 V DVCC to DVEE 3.7 V DVEE to AVEE ±0.3 V VTTI AVCC + 0.6 V VTTO AVCC + 0.6 V AMUXVCC 5.5 V Internal Power Dissipation 2.2 W ...
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AD8197A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVCC 1 PIN 1 INDICATOR IN_B0 2 IP_B0 3 AVEE 4 IN_B1 5 IP_B1 6 VTTI 7 IN_B2 8 IP_B2 9 AVEE 10 IN_B3 11 IP_B3 12 AVCC 13 IN_A0 14 IP_A0 15 AVEE ...
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Pin No. Mnemonic 24 IP_A3 26 I2C_ADDR0 27 I2C_ADDR1 28 I2C_ADDR2 29, 95 DVEE 30 PP_CH0 31 PP_CH1 32, 38, 47 DVCC 33 ON0 34 OP0 35, 41 VTTO 36 ON1 37 OP1 39 ON2 40 OP2 42 ON3 43 ...
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AD8197A Pin No. Mnemonic 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 ...
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TYPICAL PERFORMANCE CHARACTERISTICS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 ...
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AD8197A REFERENCE EYE DIAGRAM AT TP1 0.125UI/DIV AT 2.25Gbps Figure 10. Tx Eye Diagram at TP2 0.125UI/DIV AT 2.25Gbps Figure 11. Tx Eye Diagram at TP2 AD8197A DIGITAL EVALUATION PATTERN BOARD GENERATOR ...
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PERFORMANCE GRAPHS 0.6 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG 0.5 0.4 0.3 1.65Gbps EQ = 6dB 2.25Gbps 0 6dB 0 HDMI CABLE LENGTH (m) Figure 14. Jitter vs. Input ...
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AD8197A (p- (rms 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (V) Figure 20. Jitter vs. Differential Input Swing (p- ...
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THEORY OF OPERATION INTRODUCTION The AD8197A is a pin-to-pin HDMI 1.3 receive-compliant replacement for the AD8191A. The primary function of the AD8197A is to switch one of four (HDMI or DVI) single-link sources to one output. Each HDMI/DVI link consists ...
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AD8197A VTTO 50Ω 50Ω OPx DISABLE I OUT AVEE Figure 26. High Speed Output Simplified Schematic The AD8197A requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the ...
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SERIAL CONTROL INTERFACE RESET On initial power-up any point in operation, the AD8197A register set can be restored to preprogrammed default values by pulling the RESET pin low in accordance with the specifications in Table 1. During normal ...
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AD8197A I2C_SCL GENERAL CASE FIXED PART START ADDR I2C_SDA ADDR EXAMPLE I2C_SDA 1 2 READ PROCEDURE To read data from the AD8197A register set (such as a microcontroller) needs to send the appropriate control signals to the AD8197A ...
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PARALLEL CONTROL INTERFACE The AD8197A can be controlled through the parallel interface using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1. ...
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AD8197A SERIAL INTERFACE CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I The least significant bits of the AD8197A I 3.3 V (Logic (Logic 0). As soon as the serial ...
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HIGH SPEED DEVICE MODES REGISTER HS_EN: High Speed (TMDS) Channel Enable Bit Table 6. HS_EN Description HS_EN Description 0 High speed channels off, low power/standby mode 1 High speed channels on HS_CH[1:0]: High Speed (TMDS) Switch Source Select Bus Table ...
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AD8197A RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 RX_EQ[x]: High Speed (TMDS) Input X Equalization Level Select Bit Table 13. RX_EQ[x] Description RX_EQ[x] Description 0 Low equalization (6 dB) 1 High equalization (12 dB) Table 14. RX_EQ[x] Mapping RX_EQ[x] Corresponding ...
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PARALLEL INTERFACE CONFIGURATION REGISTERS The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using ...
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AD8197A HIGH SPEED DEVICE MODES REGISTER PP_EN: High Speed (TMDS) Channel Enable Bit Table 19. PP_EN Description PP_EN Description 0 High speed channels off, low power/standby mode 1 High speed channels on PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus ...
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APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197A Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197A is an HDMI/DVI switch, featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for ...
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AD8197A The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors, including: • Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors ...
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TMDS signals away from other signals and noise sources on the PCB. Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is ...
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AD8197A AD8197A and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to ...
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Power Supply Bypassing The AD8197A requires minimal supply bypassing. When powering the supplies individually, place a 0.01 μF capacitor between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO) and ground to filter out supply noise. Generally, bypass capacitors ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD8197AASTZ −40°C to +85°C 1 AD8197AASTZ-RL −40°C to +85°C AD8197A-EVALZ RoHS Compliant Part. Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I ...