AD8196ACPZ-RL Analog Devices Inc, AD8196ACPZ-RL Datasheet - Page 20

• Manufacturer Part Number: AD8196ACPZ-RL
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: HDMI/DVI Switchr

Specifications of AD8196ACPZ-RL

• Applications: DVI, HDMI Signal Switching
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8196
Layout for the TMDS Signals
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together to establish the required 100 Ω differ-
ential impedance. Enough space should be left between the
differential pairs of a given group so that the n of one pair does
not couple to the p of another pair. For example, one technique is
to make the interpair distance 4 to 10 times wider than the
intrapair spacing.
Any one group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths to minimize
interpair skew. Severe interpair skew can cause the data on the
four different channels of a group to arrive out of alignment
with one another. A good practice is to match the trace lengths
for a given group of four channels to within 0.05 inches on FR4
material.
Minimizing intra- and interpair skew becomes increasingly
important as data rates increase. Any introduced skew consti-
tutes a correspondingly larger fraction of a bit period at higher
data rates.
Though the AD8196 features input equalization and output pre-
emphasis, the length of the TMDS traces should be minimized
to reduce overall system signal degradation. Commonly used
PC board material such as FR4 is lossy at high frequencies, so
long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
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Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on
a number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. Generally, working with the PC board fabricator is
required to obtain a set of parameters to produce the desired
results.
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 Ω differential impedance. When the traces
split apart to go into a connector, for example, and are no longer
so strongly coupled, the width of the traces should be increased
to yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8196. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing dif-
ferential pairs on multiple layers, it is necessary to also reroute
the corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
in Figure 32.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 32. Example Routing of Reference Plane
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
THROUGH-HOLE VIAS