AD8196ACPZ-RL Analog Devices Inc, AD8196ACPZ-RL Datasheet - Page 15

• Manufacturer Part Number: AD8196ACPZ-RL
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: HDMI/DVI Switchr

Specifications of AD8196ACPZ-RL

• Applications: DVI, HDMI Signal Switching
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

READ PROCEDURE
To read data from the AD8196 register set, an I
as a microcontroller) needs to send the appropriate control
signals to the AD8196 slave device. The signals are controlled
by the I
the procedure, see Figure 30. The steps for a read procedure are
as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for the AD8196 to acknowledge the request.
11. The AD8196 serially transfers the data (eight bits) held in
12. Acknowledge the data from the AD8196.
GENERAL CASE
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8196 part address (seven bits). The upper six
bits of the AD8196 part address are the static value [100100]
and the LSB is set by Input Pin I2C_ADDR. This transfer
should be MSB first.
Send the write indicator bit (0).
Wait for the AD8196 to acknowledge the request.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
Wait for the AD8196 to acknowledge the request.
Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
Resend the AD8196 part address (seven bits) from Step 2.
The upper six bits of the AD8196 part address compose the
static value [100100]. The LSB is set by Input Pin I2C_ADDR.
This transfer should be MSB first.
Send the read indicator bit (1).
the register indicated by the address set in Step 5. This data
is sent MSB first.
EXAMPLE
I2C_SDA
I2C_SDA
I2C_SCL
2
C master, unless otherwise specified. For a diagram of
START
1
2
FIXED PART ADDR
ADDR ACK
R/W
3
4
2
C master (such
5
REGISTER ADDR
Figure 30. I
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2
C Read Procedure
ACK
6
7
SR
13. Do one of the following:
SWITCHING/UPDATE DELAY
There is a delay between when a user writes to the configura-
tion registers of the AD8196 and when that state change takes
physical effect. This update delay begins at the falling edge of
I2C_SCL for the last data bit transferred, as shown in Figure 29.
This update delay is register specific and the times are specified
in Table 1.
During a delay window, new values can be written to the
configuration registers but the AD8196 does not physically
update until the end of that register’s delay window. Writing
new values during the delay window does not reset the window;
new values supersede the previously written values. At the end
of the delay window, the AD8196 physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8196 immediately updates and a new
delay window begins.
a.
b.
c.
d.
FIXED PART ADDR
8
Send a stop condition (while holding the I2C_SCL
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in Figure 30).
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the write procedure (see the
previous Write Procedure section) to perform a write.
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of this procedure to perform a
read from the same address.
ADDR ACK
R/W
9 10 11
DATA
ACK
AD8196
12
STOP
13