XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 91

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Functional Description
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
84
• Internal memory
• Disk drive
• Over network
• Over RF link
Configuration
Memory
Source
Download Host
Intelligent
• Microcontroller
• Processor
• Tester
• Computer
SERIAL_OUT
Recommend
open-drain
PROG_B
driver
VCC
GND
PROG_B
V
CLOCK
INIT_B
TMS
TDO
TCK
DONE
TDI
+2.5V
JTAG
Figure 60: Slave Serial Configuration
www.xilinx.com
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
P
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Similarly, the FPGA’s HSWAP pin must be Low to
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_2
INIT_B
DONE
DOUT
TDO
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
VCCO_0
+2.5V
V
V
DS312-2_54_022305
+2.5V
R