XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 63

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Functional Description
Configuration
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glue-less
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories. Unlike Spartan-3
FPGAs, nearly all of the Spartan-3E configuration pins
become available as user I/Os after configuration.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this configu-
ration process uses a subset of the device pins, some of
which are dedicated to configuration; other pins are merely
Table 38: Spartan-3E Configuration Mode Pin Settings
56
M[2:0] mode pin
settings
Data width
Configuration memory
source
Clock source
Total I/O pins
borrowed during
configuration
Configuration mode
for downstream
daisy-chained FPGAs
Self-configuring
applications (no
external download
host)
Uses low-cost,
industry-standard
Flash
Slave Serial
oscillator
Platform
<0:0:0>
Internal
Master
Serial
Serial
Xilinx
Flash
8
Industry-standard
Internal oscillator
SPI Serial Flash
Slave Serial
<0:0:1>
Serial
SPI
13
www.xilinx.com
Industry-standard
Internal oscillator
<0:1:1>=Down
Slave Parallel
parallel NOR
<0:1:0>=Up
Byte-wide
Flash
BPI
46
borrowed and returned to the application as general-pur-
pose user I/Os after configuration completes.
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single config-
uration memory source, creating a structure called a daisy
chain.
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
38. The mode pin values are sampled during the start
microcontroller,
Platform
XCFxxP Platform
generates CCLK
Any source via
Slave Parallel
External clock
Slave Parallel
on CCLK pin
Possible using
CPU, Xilinx
Flash, which
or Memory
Byte-wide
optionally
Mapped
<1:1:0>
parallel
etc.
21
Flash,
XCFxxP Platform
microcontroller,
Platform
Any source via
generates CCLK
External clock
Slave Serial
on CCLK pin
Possible using
Slave Serial
CPU, Xilinx
Flash, which
Advance Product Specification
optionally
<1:1:1>
DS312-2 (v1.1) March 21, 2005
Serial
etc.
8
Flash,
System Ace CF
microcontroller,
Any source via
External clock
CPU, etc. and
on TCK pin
<1:0:1>
JTAG
Serial
JTAG
0
R