XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 61

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Functional Description
There are four type of general-purpose interconnect avail-
able in each channel, as shown in
below.
Long Lines
Each set of 24 long line signals spans the die both horizon-
tally and vertically and connects to one out of every six inter-
connect tiles. At any tile, four of the long lines drive or
receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given inter-
connect tile. Double lines are more connections and more
flexibility, compared to long line and hex lines.
Direct Connections
Direct connect lines route signals to neighboring tiles: verti-
cally, horizontally, and diagonally. These lines most often
drive a signal from a "source" tile to a double, hex, or long
line and conversely from the longer interconnect back to a
direct line accessing a "destination" tile.
54
Horizontal and
Vertical Long Lines
(horizontal channel
shown as an example)
Horizontal and
Vertical Hex Lines
(horizontal channel
shown as an example)
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
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Figure 47
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and described
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www.xilinx.com
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Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in
cation via the STARTUP_SPARTAN3E primitive.
Table 37: Spartan-3E Global Logic Control Signals
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted auto-
matically during the FPGA configuration process, guaran-
teeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for
figuration Images Using MultiBoot Option, page
CLK input is an alternate clock for configuration
page
Control Input
Table
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Global
91.
GSR
GTS
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37. These signals are available to the FPGA appli-
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24
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When driven High, asynchronously
places all registers and flip-flops in their
initial state (see
Asserted automatically during the FPGA
configuration process (see
page
When driven High, asynchronously
forces all I/O pins to a high-impedance
state (Hi-Z, three-state).
Dynamically Loading Multiple Con-
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91).
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Advance Product Specification
DS312-2 (v1.1) March 21, 2005
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Description
Initialization, page
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DS312-2_11_020905
DS312-2_10_022305
Start-Up,
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Start-Up,
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78. The
24).
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