XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 14

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

DS312-2 (v1.1) March 21, 2005
Advance Product Specification
OCLK1
OCLK2
PAD
Figure 6: Output DDR (without Cascade Feature)
D1
D2
From
Fabric
OCLK1
OCLK2
d
D1
D2
d+1
R
d
d+2
d+1
d+3
d+2
d+4
d+3
d+5
D
D
d+4
Q
d+6
Q
d+5
d+7
d+6
d+8
DS312-2_23_030105
d+7
d+9
PAD
www.xilinx.com
d+10
d+8
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards
Table
differential pairs to support any of the differential signaling
standards
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Con-
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. Spe-
cial care must be taken to ensure the input voltages do not
exceed V
particular V
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
OCLK1
OCLK2
From
Fabric
OCLK1
OCLK2
Figure 7: Output DDR Using Spartan-3E Cascade
PAD
D2
D1
D2 d+1
4). The majority of the I/Os also can be used to form
D1
CCO
d
(Table
CCO
D
(see
d
Q
voltage,
d+3
d+2
4).
ODDROUT1
d+1
Module 3
ODDRIN2
d+2
Table 3
Feature
d+5
d+4
d+3
for the specifications). For a
and
Functional Description
d+4
D
d+6
d+7
D
Table 4
d+5
Q
Q
d+6
list all of the
(Table 3
DS312-2_36_030105
d+9
d+8
d+7
PAD
and
d+8
7