XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 68

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Table 42: Serial Master Mode Connections (Continued)
Voltage Compatibility
The PROM’s V
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
Flash PROM’s V
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
VCCAUX supply, nominally 2.5V. See application note
XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs"
for additional information.
Supported Platform Flash PROMs
Table 43
PROM to program a single Spartan-3E FPGA. A multi-
ple-FPGA daisy-chain application requires a Platform Flash
PROM large enough to contain the sum of the various
FPGA file sizes.
Table 43: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
DONE
PROG_B
V
Pin Name
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
The FPGA’s VCCO_2 supply input and the Platform
Device
shows the smallest available Platform Flash
R
FPGA Direction
bidirectional I/O
CCINT
CCO
Open-drain
Configuration
Input
Number of
1,352,192
2,267,136
3,832,320
5,957,760
supply input must be the same volt-
supply must be either 3.3V for the
581,344
Bits
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up resistor
to 2.5V. If driving externally, use an
open-drain or open-collector driver.
Smallest Available
Platform Flash
or 2 x XCF04S
XCF01S
XCF02S
XCF04S
XCF04S
XCF08P
Description
www.xilinx.com
The XC3S1600E requires an 8 Mbit PROM. There are two
possible solutions. Either use a single 8 Mbit XCF08P par-
allel/serial PROM or cascade two 4 Mbit XCF04S serial
PROMs. The two XCF04S PROMs use a 3.3V V
ply while the XCF08P requires a 1.8V V
board does not already have a 1.8V supply available, the
two cascaded XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator gener-
ates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option.
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 44: Maximum ConfigRate Settings for Platform
Flash
Platform Flash
Part Number
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
Connects to PROM’s
chip-enable (CE) input.
Enables PROM during
configuration. Disables
PROM after configuration.
Must be High during
configuration to allow
configuration to start.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
During Configuration
3.3V, 2.5V, or 1.8V
(VCCO_2, VCCO)
3.3V or 2.5V
I/O Voltage
1.8V
Functional Description
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
configured.
Drive PROG_B Low
and release to
reprogram FPGA.
After Configuration
Table 44
CCINT
ConfigRate
Maximum
Setting
supply. If the
CCINT
shows the
25
12
25
sup-
61