5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 59

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Product and Vendor Name
A01 LVDSS FPGA AMC
Dallas Logic
Stratix IV GX/GT 40G/
100G Interlaken
HiTech Global
HD FIFO Modules
Averlogic
Broadcast Video Card
Bitec
Quad Video Board
Bitec
HDMI Receiver/Transmitter
Microtronix
Quad Link LVDS Interface
Microtronix
CX4 to HSMC Adapter
MorethanIP
Daughtercard
Daughtercard
Daughtercard
Daughtercard
Daughtercard
Daughtercard
EP4SGX530
EP4S100G5
EP1AGX60
Stratix IV
Arria GX
Device
Description
This LVDS transceiver card features the Arria GX FPGA in the F780 BGA package. The
backplane interface is user configurable to support several interface standards including
PCIe, Serial RapidIO, and GbE. The front panel VHDCI connector supports 28 transmit and
28 receive LVDS links sourced from the FPGA (and 2 clock signals for each transmit and
receive connector). Additional features include two 512-Kb x36 synchronous SRAMs, an IPMI
1.5-compliant Module Management Controller (MMC), a 32-Mb serial flash memory, two
onboard temperature sensors, USB communication and debug interface, and a 32-bit Mictor
debug connector.
This board integrates the most fundamental electrical and optical interfaces for building
200G subsystems. It implements CAUI and Interlaken high-speed serial interfaces,
industry-leading, high-speed DDR3 and QDR II+ interfaces, and high-speed parallel
interconnect for NetLogic knowledge-based processors (KBPs). The modular design enables
expansion to support legacy and emerging optical modules.
This board is designed for evaluating the AL460A HD-FIFO. It has two embedded
AL460A-7-PBF (or AL460A-13-PBF) devices operating in parallel, expanding the bus width
to 32 bits. Control signals and data bus signals are available on two 50-pin connectors. A
separate adaptor board (HSMC interface) is available for connecting the module directly to a
Cyclone III FPGA Starter Kit.
This card is designed for professional video equipment developers. The dual ASI/SD-SDI
interfaces allow access to industry-standard video transport signals. Based on the latest
adaptive cable equalizers and drivers, the ASI/SDI interfaces provide excellent noise
immunity up to cable lengths of 350 meters. A VCXO allows precise synchronization to
incoming ASI signals. A DVB-T reference design using the Bitec BVDC daughtercard and a
Cyclone III FPGA Development Kit is available.
This board is based on the Texas Instruments TVP5154 quad video decoder. The analog video
inputs include composite video and S-video. Video output is based on the Chrontel CH7010B
device, enabling single-link DVI, component analog, and composite analog outputs. The
device accepts digital, parallel video data, and clocking from the host FPGA via the HSMC
connector, which configures and monitors the device over an I
and mini-DIN output connector are provided.
This daughtercard interfaces a HDMI receiver and transmitter to your Altera FPGA
development kit using the HSMC expansion connector. The receiver also supports an analog
component video (YCbCr) interface. The card uses the Analog Device AD9889 HDMI
Transmitter and AD9880 HDMI Receiver to support HDTV formats up to 1080p at 60 Hz. The
receiver offers the flexibility of both an analog interface and an HDMI receiver integrated on
a single chip.
This daughtercard supports receive and transmit LVDS links, each consisting of five data
channels and one clock for a total of 48 LVDS channels. The standard configuration of 20
TX + 4 clk and 20 RX + 2 clk, is capable of supporting LCD display panels up to 1080p at
100/120 Hz. Onboard LVDS termination resistors can be removed to convert receiver
channels into transmitters as required to support 12- or 14-bit color applications. It is used
for capturing LVDS video data, connecting to a camera link interface, or for connecting to
LCD panels using LVDS, mini-LVDS, RSDS, and PPDS low-voltage panel interface signaling.
This is a passive daughtercard for 10GbE CX-4 copper interconnect prototyping. It features a
four-lane differential 3.125-Gbps connector (CX-4) for 10GbE IEEE 802.3ak, a 160-pin HSMC
to the main board, and compatibility with Stratix II GX mother boards that use
HSMC connectors.
Altera and Partner Development Kits
Altera Product Catalog
•
2011
2
C link. A DVI output connector
Development Kits
•
www.altera.com
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