5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 44

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Quartus II Design Software
1
Getting Started Steps
Step 1: Download free Web Edition
Step 2: Get oriented with Quartus II interactive tutorial
Step 3: Sign up for training
Design Software
42
Included in Subscription Edition only.
http://www.altera.com/support/software/download/sof-download_center.html
After installation, open the interactive tutorial at the welcome screen.
http://www.altera.com/education/training/trn-index.jsp
Altera Product Catalog
TimeQuest timing analyzer
SignalTap II embedded
logic analyzer
PowerPlay technology
EDA partners
Incremental compilation
Pin planner
Qsys
SOPC Builder
Off-the-shelf IP cores
Parallel development
in ASICs
Scripting support
Rapid Recompile
Physical synthesis
Design space explorer (DSE)
Extensive cross-probing
Optimization advisors
Chip planner
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2011
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Improves design timing closure and reduces design compilation times up to 70 percent. Supports
team-based design.
Eases the process of assigning and managing pin assignments for high-density and high pin-count designs.
Automates system development by integrating IP functions and subsystems (collection of IP functions) using a
hierarchical approach and a high-performance interconnect (based on a network-on-a-chip architecture).
Automates adding, parameterizing, and linking IP cores—including embedded processors, coprocessors,
peripherals, memories, and user-defined logic.
Lets you construct your system-level design using IP cores from Altera’s megafunction library and from
Altera’s third-party IP partners.
Allows for FPGA prototypes and HardCopy ASICs to be designed in parallel using the same design software
and IP.
Supports command-line operation and Tcl scripting, as well as GUI design.
Maximizes your productivity by reducing your compilation time by 50 percent on average (for a small design
change after a full compile). Improves design timing preservation.
Uses post placement and routing delay knowledge of a design to improve performance.
Increases performance by automatically iterating through combinations of Quartus II software settings to
find optimal results.
Provides unmatched support for cross-probing between verification tools and design source files.
Provides design-specific advice to improve design timing performance, resource usage, and
power consumption.
Reduces verification time (while maintaining timing closure) by enabling small, post placement and routing
design changes to be implemented in minutes.
Provides native Synopsys Design Constraint (SDC) support and allows you to create, manage, and analyze
complex timing constraints and quickly perform advanced timing verification.
Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering
capabilities available in an embedded logic analyzer.
Enables you to accurately analyze and optimize both dynamic and static power consumption.
Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level
simulation, signal integrity analysis, and formal verification. To see a complete list of partners, follow the link:
http://www.altera.com/products/software/partners/eda_partners/eda/index.html
www.altera.com
Quartus II Design Software Features Summary