5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 4

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Glossary
Glossary
Below is a glossary of helpful terms to bring you up to speed on Altera devices.
2
2
Adaptive logic module (ALM)
Configuration via Protocol (CvP)
Embedded HardCopy Blocks
Equivalent LE
Fractional phase-locked loops (fPLL)
Global clock networks
LE
Macrocells
Memory logic array blocks (MLABs)
On-chip termination (OCT)
Periphery clocks (PCLKs)
Plug & Play Signal Integrity
Programmable Power Technology
Real-time in-system
programming (ISP)
Regional clocks
System on a chip (SoC)
Variable-precision DSP blocks
Altera Product Catalog
Term
•
2011
•
www.altera.com
Logic building block, used by some Altera devices, which provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided
between two combinational adaptive LUTs (ALUTs).
CvP is a configuration method that enables you to configure the FPGA using industry-standard protocols.
Currently CvP supports only the PCI Express
These metal-programmable hard IP blocks deliver up to 14M ASIC gates or up to 700K additional logic
elements (LEs) to harden standard or logic-intensive applications.
Device density represented as a comparable amount of LEs, which uses the 4-input LUT as a basis.
A phase-locked loop (PLL) in the core fabric, fPLLs provide increased flexibility as an additional clocking
source for the transceiver, replacing external voltage-controlled crystal oscillators (VCXOs).
Global clocks can drive throughout the entire device, serving as low-skew clock sources for functional
blocks such as ALMs, DSP blocks, TriMatrix memory blocks, and PLLs. See regional clocks and periphery
clocks for more clock network information.
Logic building block, used by some Altera devices, that includes a 4-input LUT, a programmable register,
and a carry chain connection. See device handbooks for more information.
Similar to LEs, this is the measure of density in MAX series CPLDs.
MLABs are dual-purpose blocks, configurable as regular logic array blocks or as memory blocks.
Support for driver impedance matching and series termination, which eliminates the need for external
resistors, improves signal integrity, and simplifies board design. On-chip series, parallel, and differential
termination resistors are configurable via Quartus II software.
PCLKs are a collection of individual clock networks driven from the periphery of the device. PCLKs can be
used instead of general-purpose routing to drive signals into and out of the device.
This capability, consisting of Altera’s adaptive dispersion engine and hot socketing, lets you change
the position of backplane cards on the fly, without having to manually configure your backplane
equalization settings.
This feature automatically optimizes logic, DSP, and memory blocks for the lowest power at the required
performance. Only the blocks with critical-path logic need to be in high-performance mode; all others are
in low-power mode.
This capability allows you to program a MAX II device while the device is still in operation. The new design
only replaces the existing design when there is a power cycle to the device. This way, you can perform
in-field updates to the MAX II device at any time without affecting the operation of the whole system.
Regional clocks are device quadrant-oriented and provide the lowest clock delay and skew for logic
contained within a single device quadrant.
An SoC is an embedded system that consists of a processor, peripherals, and custom hardware integrated
on a single device.
These integrated blocks provide native support for signal processing of varying precisions—for example,
9x9, 27x27, and 18x36—in a sum or independent mode.
®
(PCIe
Definition
®
) protocol.