PAC-SYSCLK5620AV Lattice, PAC-SYSCLK5620AV Datasheet - Page 5

• Manufacturer Part Number: PAC-SYSCLK5620AV
• Description: MCU, MPU & DSP Development Tools ispCLK5620AV Design System
• Manufacturer: Lattice

Specifications of PAC-SYSCLK5620AV

• Processor To Be Evaluated: ispClock5620A
• Silicon Manufacturer: Lattice
• Silicon Core Number: IspPAC-CLK5620AV-01T100I
• Kit Contents: IspClock5620A Evaluation Board, IspDownLoad Cable, AC Adapter, User Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 4. Oscillator and High-Speed I/O
Figure 5. User Controls and Miscellaneous I/O
V33
S2.1
S2.2
S2.3
S2.4
S2.5
S2.6
S2.7
S2.8
DISABLED
FB2
PLL_BYPASS
PS0
PS1
GOE
REFSEL
OEX
OEY
S2.9
SGATE
Oscillator
0.1u
C11
closed
when
V33
Notes:
1. If OSC1 is LVCMOS type, omit R27,R28
2. Not populated
1
V33
If OSC1 is DPECL type, for external termination
EN
install R27,R28
(note 1)
OSC1
GND
6
3
VCC
RESET
S1
OUT
OUT
REFVTT J5.25
0.1u
C8
4
5
REFA+
REFA-
J8
J9
R6 1K
R27
100
FBKVTT
FBKA+
FBKA-
2
R15
2.2K
R28
100
J6
J7
J5.24
2
R16 1K
R17 1K
R18 1K
R19 1K
R20 1K
R21 1K
R22 1K
R23 1K
38
39
32
33
34
41
42
40
32
33
34
35
36
37
V33
5
REFA+
REFA-
FBKA+
FBKA-
FBKVTT
REFB+
REFB-
REFVTT
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
R26
R24
R25
680
680
680
C12
0.1u
V33
ispClock5620A
POWER
LOCK
TDO
D4
D2
D3
ispClock5620A Evaluation Board:
C11
0.1u
U1
V33
92
89
88
87
85
44
45
86
72
90
91
43
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
RESET
LOCK
TEST2
TEST1
BANK8A
BANK8B
BANK9A
BANK9B
GNDO9
GNDO8
ispPAC-CLK5620A-EV1
VCCO9
VCCO8
ispClock5620A
GNDA
VCCA
U1
30
31
67
70
69
68
63
66
65
64
TDO
TMS
TCK
TDI
0.1u
C9
C13
0.1u
C14
0.1u
73
84
82
83
FB1
FB3
FB4
VCCO
VCCO
V33
V33
BANK9A
BANK9B
BANK8A
J12
BANK8B
J13
J10
J11
Jx.7 GND
Jx.8 TCK
Jx.1 VS
Jx.2 TDO
Jx.3 TDI
Jx.4 n/c
Jx.5 plug
Jx.6 TMS