PAC-SYSTEMCLK5520 Lattice, PAC-SYSTEMCLK5520 Datasheet
PAC-SYSTEMCLK5520
Specifications of PAC-SYSTEMCLK5520
Related parts for PAC-SYSTEMCLK5520
PAC-SYSTEMCLK5520 Summary of contents
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... GND CCO ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 100-pin and 48-pin TQFP Packages ■ Applications • Circuit board common clock generation and distribution • PLL-based frequency generation • High fan-out clock buffer ...
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... Lattice Semiconductor General Description and Overview The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides sin- gle-ended or five differential clock outputs, while the ispClock5520 provides single-ended or 10 differential clock outputs. Each pair of outputs may be independently confi ...
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... Lattice Semiconductor Figure 2. ispClock5520 Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-32) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-32) JTAG INTERFACE TDI TMS LOCK RESET PLL_BYPASS SGATE GOE OUTPUT ENABLE CONTROLS LOCK DETECT 1 PHASE LOOP ...
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... Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage -0.5 to 5.5V CCD PLL Supply Voltage -0.5 to 5.5V CCA JTAG Supply Voltage -0.5 to 5.5V CCJ Output Driver Supply Voltage V CCO Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V 1 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130° ...
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... Lattice Semiconductor Performance Characteristics – Power Supply Symbol Parameter I Core Supply Current CCD I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency. ...
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... Input Pull-down Current PD I Tristate Leakage Output OLK C Input Capacitance IN 1. Applies to clock reference inputs when termination ‘open’. 2. Applies to TDI, TMS inputs. 3. Applies to REFSEL, PS0, PS1, GOE, SGATE and PLL_BYPASS. 4. Applies to all logic types when in tristated mode. 5. Applies to OEX, OEY, TCK, RESET inputs. ...
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... Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type Base Parameter( Input Adders IOI LVTTL_in LVCMOS18_in LVCMOS25_in LVCMOS33_in SSTL2_in SSTL3_in HSTL_in LVDS_in LVPECL_in Output Adders IOO LVTTL_out LVCMOS18_out LVCMOS25_out LVCMOS33_out SSTL2_out SSTL3_out HSTL_out LVDS_out LVPECL_out 1 t Output Slew Rate Adders ...
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... Lattice Semiconductor Output Test Loads Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load ispCLOCK Zo = 50Ω Figure 4. HSTL/SSTL Termination Load ispCLOCK Zo = HSTL: ~20Ω ...
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... Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance Output Resistance OUT 1. Guaranteed by characterization. Conditions V Voltage CCO Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting VCCO=3 ...
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... Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference input frequency f REF range t Reference input clock HIGH and CLOCKHI, t LOW times CLOCKLO t RINP, Input rise and fall times t FINP M M-divider range DIV N N-Divider range DIV Phase detector input frequency f PFD 2 range ...
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... Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size SKSTEP t Skew Time Accuracy SKERR 1. Skew control range is a function of VCO frequency (f ...
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... Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t TCK (BSCAN Test) Hold Time ...
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... Lattice Semiconductor Timing Diagrams Figure 7. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 8. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL State Update-IR Figure 9 ...
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... Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 640MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE, f 100 -25 -50 -75 -100 Skew Setting # Period Jitter vs. VCO Frequency V 320 400 480 VCO Frequency (MHz) ...
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... LOCK signal is asserted if the phases of the reference and feedback signals match, whereas in frequency-lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals match. The option of which mode to use is programmable and may be set using PAC-Designer software (available from Lattice’s web site at www.latticesemi.com). ...
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... From N-divider Because the selection of an optimal PLL loop filter can be a daunting task, PAC-Designer offers a set of default fil- ter settings which will provide acceptable performance for most applications. The primary criterion for selecting one of these settings is the total division factor used in the feedback path. This factor is the ratio between the VCO out- ...
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... Lattice Semiconductor chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that when the skew mode is set to ‘coarse’, the effective value of NxV must be doubled. Refer to the section titled ‘Coarse Skew Mode’ on page 30 for more details. ...
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... Lattice Semiconductor where f is the frequency of V divider the input reference frequency ref M and N are the input and feedback divider settings V is the setting of the V divider used to close the PLL feedback path fbk V is the setting of the V divider used to provide output k ...
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... Lattice Semiconductor Figure 13 shows the relative timing for a V-divider as a function of its 32 possible divisor settings (2-64) as the PLL locks. If two V-dividers are configured with the same divisor, their outputs will be synchronized. If these two V-divid- ers are fed to separate outputs, and the skew settings for these two outputs are identical, then the corresponding rising and falling edges for the two outputs will occur simultaneously ...
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... Lattice Semiconductor Figure 14. Flipping Polarity to Edge Align Two Outputs Invert /8 Output Polarity / output /8 /16 For V-divider combinations in which one or more of the V-dividers is configured to a value that is not divisible by 4 (e.g. 6), there exists the possibility that neither rising nor falling edges may align. For example, when V-divider val- ues of 6 and 12 are chosen, the two resulting outputs will have no edge alignment, as shown in Figure 15 ...
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... Lattice Semiconductor Clock reference inputs may be configured to interface to signals from the following logic families with little or no external support circuitry: • LVTTL (3.3V) • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • LVDS • LVPECL (differential, 3.3V) Each input also features internal programmable termination resistors, as shown in Figure 16 ...
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... Lattice Semiconductor Figure 17. LVCMOS/LVTTL Input Receiver Configuration Signal In No Connect No Connect HSTL, SSTL2, SSTL3 The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input pair. The ‘-’ input terminal should be tied to the appropriate V V termination supply. The positive input’ ...
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... Lattice Semiconductor Differential HSTL and SSTL HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. Figure 19 shows how ispClock5500 reference input should be configured for accepting these standards. The major difference between the differential and single-ended forms of these logic standards is that in the differen- tial cases, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are engaged and set to 50Ω ...
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... Low ESR capacitors with values ranging from 0.01 to 0.1 µF may be used for this purpose. Each bypass capacitor should be placed as close to its respec- tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated parasitic inductances ...
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... Lattice Semiconductor In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground where possible. All GNDD pins must be tied to ground, regardless of whether or not the associated bank is used. ...
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... Lattice Semiconductor ispClock5500’s internal termination resistors are not available in these modes. Also note that output slew-rate con- trol is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate. Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the polarity of each of the two output signals from each bank may be controlled independently ...
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... Thermal Management In applications where a majority of the ispClock5510 or ispClock5520’s outputs are active and operating at or near maximum output frequency (320 MHz), package thermal limitations may need to be considered to ensure a suc- cessful design. Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Management which may be obtained at www ...
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... Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced airflow present in a given design, actual die operating temperature is subject to considerable variation from that which may be theoretically predicted from package characteristics and device power dissipation. Output Enable Controls The ispClock5500 family provides the user with several options for enabling and disabling output pins, as well as suspending the output clock. In addition to providing the user with the ability to reduce the device’ ...
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... Lattice Semiconductor • GOE – global output enable • OEX, OEY – secondary output enable controls • SGATE – synchronous output control 2 Additionally, internal E CMOS configuration bits are provided for the purpose of modifying the effects of these external control pins. When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled by the OEX and OEY pins ...
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... Lattice Semiconductor grammed by the user over a range 15. The ispClock5500 family also supports both ‘fine’ and ‘coarse’ skew modes. In fine skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew varies from 390ps to 780ps. The value of one TU may be calculated from the VCO frequency (f ...
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... Lattice Semiconductor When one moves from coarse skew mode to fine skew mode, the extra divide-by-two factor is removed from between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this change, all of the V-dividers must be doubled to move the VCO back into its specified operating range and maintain consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in coarse mode has a value greater than 32, as the corresponding fi ...
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... Lattice Semiconductor Figure 29. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVPECL Output ( IOS LVTTL Output (T = 0.1ns) IOS Similarly, when one changes the slew rate of an output, the output slew rate adders (t the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are measured. For example, in the case of outputs confi ...
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... PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 30 provides access to all configurable ispClock5500 elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, confi ...
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... Input and out- put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5500 for a given application. (Figure 31). Part Number PAC-SYSTEMCLK5520 PACCLK5520-EV ispClock5500 Family Data Sheet 2 CMOS memory of the ispClock5500. This consists of ® ...
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... Lattice Semiconductor Figure 31. Download from a PC PAC-Designer Software ispClock5500 Family Data Sheet Other System Circuitry ispDownload Cable (6') 4 ispClock5500 Device 35 ...
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... Lattice Semiconductor IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispClock5500 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispClock5500 both as a serial programming interface, and for boundary scan test purposes. A brief description of the ispClock5500 JTAG interface follows. For complete details of the reference specifi ...
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... Lattice Semiconductor Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state ...
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... The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The bit code for this instruction is defined by Lattice as shown in Table 8. The EXTEST (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc- tion is defi ...
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... E Configured In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5520. These instructions are primarily used to interface to the various user registers and the E volatile memory. Additional instructions are used to control or monitor other features of the device, including bound- ary scan operations ...
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... Lattice Semiconductor VERIFY – This instruction loads data from the E shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value of the address register. The device must already be in program- ming mode for this instruction to execute. DISCHARGE – ...
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... Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ‘ ...
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... VCCO pin may be left unconnected or preferably should be tied to ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uF as close to its VCCO and GNDO pins as is practical. ...
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... VCCD, GNDD – These pins provide digital supply and ground for the ispClock5500 family’s internal digital circuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. to improve noise immunity it is suggested that the supply to the VCCD pins be isolated with ferrite beads. ...
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... DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS. 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. ...
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... DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS. 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. ...
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... Lattice Semiconductor Part Number Description ispPAC-CLK55XX XXXX X Device Family Device Number CLK5510 CLK5520 Ordering Information Conventional Packaging Part Number ispPAC-CLK5510V-01T48C ispPAC-CLK5520V-01T100C Part Number ispPAC-CLK5510V-01T48I ispPAC-CLK5520V-01T100I Lead-Free Packaging Part Number ispPAC-CLK5510V-01TN48C ispPAC-CLK5520V-01TN100C Part Number ispPAC-CLK5510V-01TN48I ispPAC-CLK5520V-01TN100I Commercial Clock Outputs Supply Voltage 10 3. ...
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... Lattice Semiconductor Package Options ispClock5510: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispClock5500 Family Data Sheet ispPAC CLK5510V-01T48C VCCJ TDO LOCK VCCD GNDO_4 BANK_4A BANK_4B VCCO_4 GNDO_3 BANK_3A BANK_3B VCCO_3 ...
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... VCCO_1 7 BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 18 VCCO_4 19 BANK_4B 20 BANK_4A 21 GNDO_4 22 n/c 23 n/c 24 n/c 25 ispPAC-CLK5520V-01T100C 48 ispClock5500 Family Data Sheet 75 n/c 74 VCCJ 73 TDO 72 LOCK 71 VCCD 70 GNDO_9 69 BANK_9A 68 BANK_9B 67 VCCO_9 66 GNDO_8 65 BANK_8A 64 BANK_8B 63 VCCO_8 62 GNDO_7 61 BANK_7A 60 BANK_7B 59 VCCO_7 58 ...