PAC-SYSCLK5620AV Lattice, PAC-SYSCLK5620AV Datasheet - Page 3

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PAC-SYSCLK5620AV

Manufacturer Part Number
PAC-SYSCLK5620AV
Description
MCU, MPU & DSP Development Tools ispCLK5620AV Design System
Manufacturer
Lattice
Datasheet

Specifications of PAC-SYSCLK5620AV

Processor To Be Evaluated
ispClock5620A
Silicon Manufacturer
Lattice
Silicon Core Number
IspPAC-CLK5620AV-01T100I
Kit Contents
IspClock5620A Evaluation Board, IspDownLoad Cable, AC Adapter, User Documentation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 2. I/O Connections, Controls and Indicators
Controls and Indicators
A 12-position dipswitch (S2) is provided on the evaluation board (Figure 2) for the purpose of setting device inputs
and programming the VCCO power supply for the BANK8 and BANK9 outputs. The following table shows the
options controlled by each switch:
Table 1. User Configuration Functions
Each of the switch positions used to control logic inputs (positions 1-8) pulls its respective control signal HIGH
when it is turned on. Each of these switch outputs is connected to the device through a 1K Ω resistor. This feature
allows external CMOS logic control signals applied to the J5 header connector to over-ride the on-board switch set-
tlings.
Position
10
11
12
1
2
3
4
5
6
7
8
9
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
OSC DIS
BANK8 and BANK9 VCCO Programming
Function (when ON)
3
ispClock5620A Evaluation Board:
ispPAC-CLK5620A-EV1

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