PAC-SYSCLK5620AV Lattice, PAC-SYSCLK5620AV Datasheet - Page 4

• Manufacturer Part Number: PAC-SYSCLK5620AV
• Description: MCU, MPU & DSP Development Tools ispCLK5620AV Design System
• Manufacturer: Lattice

Specifications of PAC-SYSCLK5620AV

• Processor To Be Evaluated: ispClock5620A
• Silicon Manufacturer: Lattice
• Silicon Core Number: IspPAC-CLK5620AV-01T100I
• Kit Contents: IspClock5620A Evaluation Board, IspDownLoad Cable, AC Adapter, User Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Switch position 9 (OSC DIS) is used to control the evaluation board’s on-board clock oscillator. When this switch is
set to the OFF position the on-board 100MHz oscillator is active and when it is the ON position it is disabled. Dis-
abling the on-board oscillator is desirable when an external clock source is used as an input reference signal
because doing so reduces the jitter measured at the board’s output. Note that if the on-board source is selected
(REFSEL switch = ON) the on-board clock must not be disabled.
Switch positions 10-12 are used to program the VCCO supply for output banks 8 and 9. When all of these switches
are OFF, the default supply VCCO supply is 3.3V. The following table shows the switch configurations needed to
develop standard supply voltages:
Table 2. VCCO Programming Switch (S2) Configurations
A reset switch (S1) is provided on the evaluation board which pulls the RESET input pin HIGH when it is
depressed, re-initializing the ispClock5620A. After changing profiles or reprogramming the ispClock5620A it is nec-
essary to reset the device to obtain a stable clock output.
Several LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging. LED
D2 (red) indicates that the on-board 3.3V supply is powered up. LED D3 (yellow) is connected to the
ispClock5620A’s TDO line, and will briefly flash when downloading, indicating that download data has made it to
the device. Finally, when LED D4 (green) is lit, this indicates that the ispClock5620A’s PLL is in a ‘locked’ state.
Schematics
The following three figures comprise the schematics for the ispPAC-CLK5620A-EV1 evaluation board. Figure 3
shows the on-board power-conditioning circuitry, Figure 4 shows the high-speed interconnects and on-board oscil-
lator circuitry, while Figure 5 shows all the logic control signals and indicators.
Figure 3. On-Board Power Supplies
Power Jack
GND BANANA
+5V BANANA
5mm
(BLACK)
(RED)
S2.10
Output Voltage vs. Switch Settings
OFF
OFF
OFF
ON
S2.11
J2
J1
OFF
OFF
OFF
J3
ON
S2.12
OFF
OFF
OFF
ON
D1
100uF
3.30 V
VCCO
2.50 V
1.80 V
C1
1.50 V
0.1uF
0.1uF
C4
C6
OFF
OFF
OFF
ON
10
S2 Switch Position
3
4
3
4
IN
IN
IN
IN
OFF
OFF
OFF
ON
1
1
11
TPS77733
TPS77701
2
2
U2
U3
4
OUT
OUT
OUT
OUT
FB
OFF
OFF
OFF
ON
12
5
6
5
6
7
100K
1%
R1
ispClock5620A Evaluation Board:
VCCO
3.3V
1.5V
1.8V
2.5V
S2.10
S2.11
S2.12
0.1uF
C5
R4 73.2K 1%
R5 31.6K 1%
R2 178K 1%
R3 300K 1%
ispPAC-CLK5620A-EV1
10 uF
C2
0.1uF
C7
10uF
C3
VCCO
V33