IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 3

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1. About This MegaCore Function
Chapter 2. Functional Description
Chapter 3. Getting Started
Altera Corporation
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–1
Features ................................................................................................................................................... 1–2
General Description ............................................................................................................................... 1–2
Performance and Resource Utilization ............................................................................................... 1–4
Block Description ................................................................................................................................... 2–1
Device-Level Configuration ............................................................................................................... 2–12
Interfaces ............................................................................................................................................... 2–16
Signals ................................................................................................................................................... 2–22
Parameters ............................................................................................................................................ 2–28
MegaCore Verification ........................................................................................................................ 2–33
Design Flow ............................................................................................................................................ 3–1
RLDRAM II Controller Walkthrough ................................................................................................. 3–2
Simulate the Example Design ............................................................................................................ 3–11
OpenCore Plus Evaluation .............................................................................................................. 1–4
Control Logic .................................................................................................................................... 2–2
Datapath ............................................................................................................................................ 2–3
OpenCore Plus Time-Out Behavior ............................................................................................. 2–12
PLL Configuration ......................................................................................................................... 2–12
Example Design .............................................................................................................................. 2–14
Constraints ...................................................................................................................................... 2–16
Initialization .................................................................................................................................... 2–16
Writes ............................................................................................................................................... 2–17
Reads ................................................................................................................................................ 2–19
Refreshes .......................................................................................................................................... 2–21
Memory ............................................................................................................................................ 2–29
Timing .............................................................................................................................................. 2–31
Project Settings ................................................................................................................................ 2–32
Simulation Environment ............................................................................................................... 2–33
Hardware Testing ........................................................................................................................... 2–33
Create a New Quartus II Project .................................................................................................... 3–3
Launch IP Toolbench ....................................................................................................................... 3–4
Step 1: Parameterize ......................................................................................................................... 3–5
Step 2: Constraints ............................................................................................................................ 3–7
Step 3: Set Up Simulation ................................................................................................................ 3–8
Step 4: Generate ................................................................................................................................ 3–8
MegaCore Version 9.1
Contents
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