IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 11

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Block
Description
Figure 2–1. RLDRAM II Controller Block Diagram
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
November 2009
dqs_delay_ctrl[] ( Note 4)
reset_addr_cmd_clk_n
capture_clk[] ( Note 4)
You can edit the rldramii_ prefix in IP Toolbench.
The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and
<signal>_1 are present.
Non-DQS mode only.
DQS mode only.
capture_clk ( Note 3 )
reset_read_clk_n[]
Figure
local_rdata_valid[]
addr_cmd_clk
local_bank_addr[]
local_refresh_req
local_wdata_req
reset_clk_n
local_write_req
local_init_done
local_read_req
non_dqs_
2–1:
local_wdata[]
write_clk
local_rdata[]
local_addr[]
local_dm[]
clk
Figure 2–1
diagram.
shows the RLDRAM II Controller MegaCore function block
Control Logic
(Encrypted)
MegaCore Version 9.1
RLDRAM II Controller
Note (1)
2. Functional Description
,
(2)
Datapath
rldramii_dq[]
rldramii_q[]
rldramii_qk[]
rldramii_qvld[]
rldramii_a_0[]
rldramii_ba_0[]
rldramii_clk[]
rldramii_clk_n[]
rldramii_cs_n_0
rldramii_d[]
rldramii_dm[]
rldramii_ref_n_0
rldramii_we_n_0
2–1