IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 18

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Block Description
Figure 2–5. DQS Group Block Diagram—DQS Mode, SIO Devices
Notes to
(1)
(2)
(3)
(4)
2–8
RLDRAM II Controller MegaCore Function User Guide
This figure shows the logic for one Q output and one D input only.
All clocks are clk, unless marked otherwise.
Bus width W is dependent on the Q per DQS parameter.
Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the Q pin.
This inversion is automatic if you use an altdq megafunction for the Q pins.
Figure
control_wdata_valid
control_doing_wr
control_wdata
control_rdata
capture_clk
2–4:
2W
2W
Datapath Example
Figure 2–6
controller and memory configuration has the following parameters:
■
■
■
Note 4
W
DQS mode
Two 18-bit CIO RLDRAM II devices. Each RLDRAM II device has
two rldramii_qk[] data strobes, each associated with 9-bits of
data
36-bit RLDRAM II interface, which requires a 72-bit datapath
interface
W
D
D
D
EN
EN
shows an example datapath. The example RLDRAM II
W
MegaCore Version 9.1
Q
Q
Q
W
dq_capture_clk
write_clk
Q
D
dq_oe
D
D
Q
Q
Q
Q
D
D
Note
D
0
1
Q
(1), (2),
DQS Delay
(3)
Altera Corporation
November 2009
DQS
D
Q