IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 71

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
1
The timing diagrams in this chapter are for QDR II SRAM with the following
parameters:
■
■
■
■
Figure 9–1
You can set the avl_w_size to 0x2 and hold avl_w_addr constant at 0x0 to perform the
same back-to-back write.
Figure 9–1. Back-to-Back Writes
Figure 9–2
×18
Half rate
Burst length 4
Latency 2.5
shows back-to-back write to addresses 0 and 1.
shows back-to-back read from addresses 0 and 1.
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
External Memory Interface Handbook Volume 3
9. Timing Diagrams