IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 39

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Controller
Signal Description
Table 5–2. Avalon-MM Slave Read Signals (Part 2 of 2)
Table 5–3. Avalon-MM Slave Write Signals
December 2010 Altera Corporation
avl_r_rdata
avl_r_size
avl_w_ready
avl_w_write_req
avl_w_addr
avl_w_wdata
avl_w_be
avl_w_size
Avalon-MM Slave Write Interface
Signal
Signal
1
The data width of the Avalon-MM interface is restricted to powers of two when using
SOPC Builder or Qsys. Non-power-of-two data widths are supported when using the
MegaWizard Plug-In Manager.
Table 5–3
log_2(MAX_BURST_SI
log_2(MAX_BURST_SI
16, 18, 36, 72, 144
18, 36, 72, 144
shows the list of signals of the controller’s Avalon-MM slave write interface.
2,4,8,16
ZE) + 1
ZE) + 1
Width
Width
≤
1
1
20
Direction
Direction
Out
Out
In
In
In
In
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
readdata
—
waitrequest_n
write
address
writedata
byteenable
—
Avalon-MM Signal Type
Avalon-MM Signal Type
External Memory Interface Handbook Volume 3
Description
Description
—
—
—
—
—
—
—
—
5–3