IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 15

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
SOPC Builder Design Flow
SOPC Builder Design Flow
December 2010 Altera Corporation
Specify Parameters
f
f
You can use SOPC Builder to build a system that includes your customized IP core.
You easily can add other components and quickly create an SOPC Builder system.
SOPC Builder automatically generates HDL files that include all of the specified
components and interconnections. SOPC Builder defines default connections, which
you can modify. The HDL files are ready to be compiled by the Quartus II software to
produce output files for programming an Altera device. SOPC Builder generates a
simulation testbench module for supported cores that includes basic transactions to
validate the HDL files.
Builder system.
Figure 2–3. SOPC Builder System
For more information about system interconnect fabric, refer to the System Interconnect
Fabric for Memory-Mapped Interfaces and System Interconnect Fabric for Streaming
Interfaces chapters in the
Specifications.
For more information about SOPC Builder and the Quartus II software, refer to the
SOPC Builder Features and Building Systems with SOPC Builder sections in the
Builder User Guide
To specify IP core parameters in the SOPC Builder flow, follow these steps:
SOPC Builder System
and to Quartus II Help.
Figure 2–3
Peripheral 1
SOPC Builder User Guide
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
shows a block diagram of an example SOPC
System Interconnect Fabric
Testbench Module
Altera IP Core
Altera IP Core
Peripheral 2
Simulation
Instance
and to the
External Memory Interface Handbook Volume 3
Peripheral 3
Avalon Interface
SOPC
2–5