IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 43

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Block Description
Table 6–2. Clocks—Full-Rate Designs (Part 2 of 2)
December 2010 Altera Corporation
Clock
read_capture_clk
Notes for
(1) For memory frequencies >240 MHz.
(2) For memory frequencies <=240 MHz.
(3) For parameterizations with interface width >36, pll_mem_clk and pll_write_clk are assigned to use the global network.
Table
Address and Command Datapath
6–2:
The UniPHY uses an active-low, asynchronous assert and synchronous deassert reset
scheme. The global reset signal resets the PLL in the PHY and the rest of the system
waits in reset until after the PLL is locked. The number of synchronization pipeline
stages is 4.
The memory controller controls the read and write addresses and commands to meet
the memory specifications. The PHY simply passes the address and command
received from the memory controller to the memory device. The PHY is also
indifferent to address or command; the circuitry is the same for both.
The address and command datapath outputs are connected to the inputs of the
address and command I/Os . An ALTDDIO_OUT megafunction converts the
addresses from SDR to DDR. An ALTDDIO_OUT megafunction with an ALTIOBUF
megafunction delivers a pair of address and command clock to the memory.
Figure 6–2
requires the registry-and- address-swapping circuitry inside the dotted box when it is
operating in half-rate (HR) mode with odd write latency (WL). In full-rate mode,
ddio_address_h and ddio_addesss_l are the same.
Figure 6–2. Address and Command Datapath
Source
Memory
Full
addr_cmd_clk
illustrates the address and command datapath. The controller only
afi_address
Clock
Rate
pll_afi_clk
90°
Phase
Local
Clock Network
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Only if HR and WL are odd
Type
A continuous running clock from the
memory device for capturing read data.
External Memory Interface Handbook Volume 3
ddio_address_h
ddio_address_l
Description
DDIO
DDIO
6–3