IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 20

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–10
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Differences in UniPHY IP Generated with HardCopy Migration Support
■
You can use the example top-level project that is generated when you turn on
HardCopy Migration as a guide to help you connect the necessary signals in your
design.
When you generate a UniPHY memory interface for HardCopy device support,
certain features in the IP are enabled that do not exist when you generate the IP core
for only the FPGA. This section discusses those additional enabled features.
ROM Loader for Designs Using Nios II Sequencer
An additional ROM loader is intantiated in the design for UniPHY designs that use
the Nios II sequencer. The Nios II sequencer instruction code resides in RAM on either
the HardCopy or FPGA device.
When you target only an FPGA device, the RAM is initialized when the device is
programmed; however, HardCopy devices are not programmed and therefore the
RAM cannot be initialized in this fashion. Instead, the Nios II sequencer instruction
code must be stored in an external, non-volatile, ROM that loads the Nios II sequencer
RAM through a ROM loader. You must attach the ROM loader to the appropriate pins
connected to the external non-volatile ROM.
Table 2–1
wrapper to expose the ROM loader utilized by the Nios II-based sequencer within the
DDR2 or DDR3 PHY.
Table 2–1. Top-level Ports that Connect to External ROM for Loading Nios II Code Memory (Part
1 of 2)
hc_rom_config_clock
hc_rom_config_datain
hc_rom_config_rom_data_
ready
hc_rom_config_init
hc_rom_config_init_busy
f
Ensure that you place all memory interface pins close together. If, for example,
address pins are located far away from data pins, closing timing might be difficult.
summarizes the ports exposed at the top level of the PHY+Controller
For information about PLL megafunctions, refer to the
(ALTPLL) Megafunction User Guide
Reconfiguration (ALTPLL_RECONFIG) Megafunctions User
information about DLL megafunctions, refer to the
ALTDQ_DQS Megafunctions User
Port Name
Input
Input
Input
Input
Output
Direction
Guide.
and the
Write clock for the ROM loader. This clock
is the write clock for the Nios II code
memory.
Data input from external ROM.
Asserts to the code memory loader that
the word of memory is ready to be loaded.
Signals that the Nios II code memory is
being loaded from the external ROM.
Remains asserted throughout initialization
and becomes inactive when initialization
is complete. soft_reset_n can be
issued after hc_rom_config_init_busy
is deasserted.
Phase-Locked Loops
HardCopy Migration Design Guidelines
December 2010 Altera Corporation
ALTDLL and
Description
Phase-Locked Loop
Chapter 2: Getting Started
Guide. For