IPR-PCI/T64 Altera, IPR-PCI/T64 Datasheet - Page 7
IPR-PCI/T64
Manufacturer Part Number
IPR-PCI/T64
Description
IP CORE Renewal Of IP-PCI/T64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/T64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Contents
Chapter 4. Testbench
Altera Corporation
Target Mode Operation ...................................................................................................................... 3–44
Master Mode Operation ..................................................................................................................... 3–88
Host Bridge Operation ...................................................................................................................... 3–127
64-Bit Addressing, Dual Address Cycle (DAC) ............................................................................ 3–131
General Description ............................................................................................................................... 4–1
Interrupt Pin Register .................................................................................................................... 3–43
Minimum Grant Register .............................................................................................................. 3–43
Maximum Latency Register .......................................................................................................... 3–44
Target Read Transactions .............................................................................................................. 3–48
Target Write Transactions ............................................................................................................. 3–63
Target Transaction Terminations ................................................................................................. 3–77
Additional Design Guidelines for Target Transactions ............................................................ 3–88
PCI Bus Parking .............................................................................................................................. 3–92
Master Read Transactions ............................................................................................................. 3–93
Master Write Transactions .......................................................................................................... 3–108
Abnormal Master Transaction Termination ............................................................................. 3–125
Using the PCI MegaCore Function as a Host Bridge .............................................................. 3–127
Target Mode Operation ............................................................................................................... 3–131
Master Mode Operation .............................................................................................................. 3–134
Memory Read Transactions ..................................................................................................... 3–48
I/O Read Transactions ............................................................................................................. 3–61
Configuration Read Transactions ........................................................................................... 3–62
Memory Write Transactions .................................................................................................... 3–63
I/O Write Transactions ............................................................................................................ 3–75
Configuration Write Transactions .......................................................................................... 3–76
Retry ............................................................................................................................................ 3–77
Disconnect .................................................................................................................................. 3–79
Target Abort ............................................................................................................................... 3–86
Design Consideration ............................................................................................................... 3–92
Memory Read Transactions ..................................................................................................... 3–93
I/O & Configuration Read Transactions ............................................................................. 3–107
Memory Write Transactions .................................................................................................. 3–108
I/O & Configuration Write Master Transactions ............................................................... 3–124
Latency Timer Expires ............................................................................................................ 3–125
Retry .......................................................................................................................................... 3–125
Disconnect Without Data ....................................................................................................... 3–126
Disconnect with Data ............................................................................................................. 3–126
Target Abort ............................................................................................................................. 3–126
Master Abort ............................................................................................................................ 3–126
PCI Configuration Read Transaction from the pci_mt64 Local Master Device to the Internal
Configuration Space ............................................................................................................... 3–127
PCI Configuration Write Transaction from the pci_mt64 Local Master Device to the Internal
Configuration Space ............................................................................................................... 3–129
64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction ................................ 3–132
64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction ............................ 3–134
PCI Compiler Version 10.1
PCI Compiler User Guide
vii
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