IPR-PCI/T64 Altera, IPR-PCI/T64 Datasheet - Page 206
IPR-PCI/T64
Manufacturer Part Number
IPR-PCI/T64
Description
IP CORE Renewal Of IP-PCI/T64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/T64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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64-Bit Addressing, Dual Address Cycle (DAC)
3–132
PCI Compiler User Guide
64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction
Figure 3–48
cycle target read transaction.
Figure
the previous paragraph). Also, both lt_tsr[1..0] signals are asserted
to indicate that the BAR0 and BAR1 address range of pci_mt64 and
pci_t64 matches the current transaction address. In addition, the
current transaction upper 32-bit address is latched on l_adro[63..32],
and the lower 32-bit address is latched on l_adro[31..0].
1
3–7, except that
All 32-bit addressing transactions described in
Operation” on page 3–131
transactions, except for the differences described in the previous
paragraph.
PCI Compiler Version 10.1
shows the waveform for a 64-bit address, 64-bit data single-
Figure 3–48
Figure 3–48
has two address phases (described in
are applicable for 64-bit addressing
is exactly the same as
Altera Corporation
“Target Mode
January 2011
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