IPR-PCI/T64 Altera, IPR-PCI/T64 Datasheet - Page 197
IPR-PCI/T64
Manufacturer Part Number
IPR-PCI/T64
Description
IP CORE Renewal Of IP-PCI/T64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/T64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
January 2011
Mismatched Bus Width Burst Memory Write Master Transactions
This section is only applicable to the pci_mt64 MegaCore function.
Figure 3–45
target cannot transfer 64-bit transactions. In this transaction, the local-
side master interface requests a 64-bit transaction by asserting
lm_req64n. The pci_mt64 function asserts req64n on the PCI side.
However, the PCI target cannot transfer 64-bit data, and therefore does
not assert ack64n in clock cycle 7. Because this is the case, the upper
address ad[63..32] and the upper command/byte enables
cben[7..4] are invalid.
In this case, the PCI function transfers 64 bits of data from the local side
l_adi[63..0] bus and automatically transfers 32-bit data on the PCI
side. The function automatically inserts wait states on the local side by
deasserting the lm_ackn signal as necessary.
Also, because the PCI side is 32 bits wide and the local side is 64 bits wide,
the pci_mt64 function assumes that the transactions are within 64-bit
boundaries. Therefore, the pci_mt64 function registers l_adi[63..0]
on the local side and transfers the lower 32-bit data word on
l_adi[31..0] on the PCI side first, and the upper 32-bit data word on
l_adi[63..32] afterwards.
PCI Compiler Version 10.1
shows the same transaction as in
Figure
Functional Description
3–38, but the PCI
3–123
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