IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 335

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Configuration write
Memory read multiple
Dual address cycle
Memory read line
Memory write and invalidate
Table 8–2. PCI Testbench PCI Bus Transaction Support (Part 2 of 2)
Transactions
Table 8–3
transactor and the local master respond to the target terminations by
terminating the transaction gracefully and releasing the PCI bus.
Master Transactor (mstr_tranx)
The master transactor simulates the master behavior on the PCI bus. It
serves as an initiator of PCI transactions for Altera PCI testbench. The
master transactor has three main sections:
■
■
■
PROCEDURES and TASKS Sections
The PROCEDURES (VHDL) and TASKS (Verilog HDL) sections define
the events that are executed for the user commands supported by the
master transactor. The events written in the PROCEDURES and TASKS
sections follow the phases of a standard PCI transaction as defined by the
PCI Local Bus Specification, Revision 3.0, including:
■
■
■
■
Target abort
Target retry
Target disconnect
Master Transactor Target Transactor
Table 8–3. PCI Testbench Target Termination Support
PROCEDURES (VHDL) or TASKS (Verilog HDL)
INITIALIZATION
USER COMMANDS
Address phase
Turn-around phase (read transactions)
Data phases
Turn-around phase
Features
v
shows the testbench's target termination support. The master
PCI Compiler Version 10.1
Master Transactor
v
v
v
v
v
v
v
Local Master
PCI Compiler User Guide
Target Transactor
v
v
Local Target
Testbench
8–5