IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 149

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–21. I/O Write Transaction
Altera Corporation
January 2011
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_beno[3..0]
lt_tsr[11..0]
(1) ack64n
cben[3..0]
lt_framen
ad[31..0]
devseln
lt_dxfrn
lt_ackn
framen
lt_rdyn
stopn
irdyn
trdyn
par
clk
1
2
000
Adr
3
I/O Write Transactions
I/O write transactions by definition are 32 bits.
sample I/O write transaction. The sequence of events is the same as 32-
bit single-cycle memory write transactions. The main distinction between
the two transactions is the command on the lt_cmdo[3..0] bus.
1
3
Adr-PAR
The PCI MegaCore functions do not ensure that the combination
of the ad[1..0] and cben[3..0] signals is valid during the
address phase of an I/O transaction. Local side logic should
implement this functionality if performing I/O transactions.
Refer to the PCI Local Bus Specification, Revision 3.0 for more
information on handling invalid combinations of these signals.
4
PCI Compiler Version 10.1
BE0_L
D0_L
5
102
Adr
3
D0-L-PAR
6
BE0_L
7
D0_L
502
8
Figure 3–21
Functional Description
9
000
10
shows a
11
3–75