IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 135

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–13. I/O Read Transaction
Altera Corporation
January 2011
l_adro[31..0]
l_cmdo[3..0]
l_beno[3..0]
l_adi[31..0]
lt_tsr[11..0]
cben[3..0]
lt_framen
ad[31..0]
devseln
lt_dxfrn
framen
lt_ackn
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
2
I/O Read Transactions
I/O read transactions by definition are 32 bits wide.
sample I/O read transaction. The sequence of events is the same as 32-bit
single-cycle memory read transactions. The main distinction between the
two transactions is the command on the lt_cmdo[3..0] bus. In
Figure
that detected the address hit is BAR1. Additionally, during an I/O
transaction l_ldat_ackn and l_hdat_ackn are not relevant.
1
000
Adr
2
3
3–13, lt_tsr[11..0] indicates that the base address register
The PCI MegaCore functions do not ensure that the combination
of the ad[1..0] and cben[3..0] signals is valid during the
address phase of an I/O transaction. Local side logic should
implement this functionality if performing I/O transactions.
Refer to the PCI Local Bus Specification, Revision 3.0 for more
information on handling invalid combinations of these signals.
Adr-PAR
PCI Compiler Version 10.1
4
Z
Z
5
BE0_L
6
102
D0_L
Adr
2
BE0_L
7
D0_L
8
D0-L-PAR
Functional Description
502
Figure 3–13
9
000
10
shows a
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