IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 229

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Local Master
The DMA engine triggers the local master. The local master can perform
32- and 64-bit memory read/write transactions with the LPM RAM block
and 32-bit single-cycle I/O read/write transactions with an I/O register
defined in the local master. The local master uses prefetch logic for burst
memory write transactions and uses the last_gen block to generate the
lm_lastn signal for the pci_mt64 and pci_mt32 MegaCore functions.
The local master ignores byte enables for all memory and I/O
transactions.
Refer to the master transactor (mstr_tranx) source code in the
<path>\pci_compiler\megawizard_flow\testbench\<HDL
language>\<PCI MegaCore function>\example directory for examples of
PCI transactions using the Altera PCI MegaCore function as a master.
lm_lastn Generator
This module generates the lm_lastn signal for the local master when the
reference design is in master mode. The lm_lastn signal is a local-side
master interface control signal that is used to request the end of the
current transaction.
Refer to
on the lm_lastn signal.
Prefetch
This module is used to prefetch the data from the LPM RAM block during
burst target read transactions and burst master write transactions.
LPM RAM
This module is used to instantiate 1 KByte of RAM for the reference
design. LPM RAM is accessible by both local target and local master. The
Local target and local master ignore byte enables for all memory
transactions.
“Master Local-Side Signals” on page 3–24
PCI Compiler Version 10.1
PCI Compiler User Guide
for more information
Testbench
4–19