IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 257

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 6–1. PCI-Avalon Bridge Burst Transfer with Multiple Pending Reads
Altera Corporation
January 2011
Agent 0
Read
Address 0x4
Agent 1
Read
Address 0xC
Master/
Agent 1
Master/
Agent 0
Arbiter
Target
Target
Bus
PCI
PCI
PCI
PCI
Bus
MegaCore
Function
PCI
In contrast, the same two reads will complete in the following sequence if
multiple pending read transactions are not allowed:
1.
2.
3.
4.
5.
Burst Transfers with Concurrent Transactions
PCI Agent 0 requests a read transaction (R0) to address 0x4. The
PCI-Avalon bridge issues a PCI retry, stores the necessary
information from the R0 transaction, and begins to retrieve the
requested data from the Avalon-MM peripheral.
Before the R0 transaction completes, PCI Agent 1 requests a read
transaction (R1) to address 0xC. Because the PCI-Avalon bridge is
currently servicing the R0 transaction, it simply issues a retry in
response to R1 and continues to retrieve the data for R0. In this case,
no information about R1 is stored in the PCI-Avalon bridge.
At some point the data for R0 is returned by the Avalon-MM
peripheral. Meanwhile, all read transactions are automatically
retried by the PCI-Avalon bridge.
PCI Agent 0 reissues the R0 transaction, and the PCI-Avalon bridge
provides the requested data and completes the R0 transaction.
At a later time, PCI Agent 1 attempts R1 again. The PCI-Avalon
bridge issues a PCI retry, stores the necessary information from the
R1 transaction, and begins to retrieve the requested data the from
Avalon-MM peripheral.
Controller
Target
PCI
PCI Compiler Version 10.1
PCI-Avalon Bridge
PCI-Avalon Bridge
Rd Addr 0x4
Rd Addr 0xC
Pending Read Buffer
Prefetchable
Bridge
Logic
Rd Data
Rd Data
Prefectable
Avalon
Master
Interconnect
System
Fabric
Parameter Settings
Peripheral #1
Peripheral #2
Avalon
Avalon
Slave
Slave
6–7