PIC16F872-E/SO Microchip Technology, PIC16F872-E/SO Datasheet - Page 74

• Manufacturer Part Number: PIC16F872-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F872
FIGURE 9-17:
9.2.15
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 9-18).
FIGURE 9-18:
DS30221C-page 72
BRG overflow,
release SCL.
If SCL = 1, load BRG with
SSPADD<6:0> and start count
to measure high time interval.
SCL
SDA
CLOCK ARBITRATION
Note: T
SCL
SDA
Write to SSPCON2,
Falling edge of
9th clock
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
= one baud rate generator period.
ACK
set PEN
T
BRG
BRG overflow occurs,
release SCL. Slave device holds SCL low.
SDA asserted low before rising edge of clock
to setup STOP condition.
T
T
BRG
BRG
T
BRG
T
SCL brought high after T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
P
T
BRG
9.2.16
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the SSP interrupt is enabled).
9.2.17
A RESET disables the SSP module and terminates the
current transfer.
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
SLEEP OPERATION
EFFECTS OF A RESET
T
BRG
SCL = 1, BRG starts counting
clock high interval
© 2006 Microchip Technology Inc.
2
C module can receive
BRG
OSC
4).