PIC16F872-E/SO Microchip Technology, PIC16F872-E/SO Datasheet - Page 62

• Manufacturer Part Number: PIC16F872-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F872
TABLE 9-2:
9.2.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 9-7).
FIGURE 9-6:
DS30221C-page 60
SDA
SCL
SSPIF
Note:
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
A7 A6 A5 A4 A3 A2 A1
1
Slave Transmission
SSPOV
2
Receiving Address
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
3
I
4
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
SSPSR
7
R/W=0
8
ACK
9
Yes
Yes
No
No
D7
1
SSPBUF
D6
2
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (Not ACK), then the
data transfer is complete. When the Not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then, the SCL pin should be enabled
by setting the CKP bit.
Generate ACK
D1
7
Pulse
D0
8
Yes
No
No
No
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
© 2006 Microchip Technology Inc.
ACK is not sent
(SSP Interrupt occurs
D3
5
D2
6
Set bit SSPIF
if enabled)
D1
7
Yes
Yes
Yes
Yes
D0
8
ACK
Not
9
transfer
Bus Master
terminates
P