PIC16F872-E/SO Microchip Technology, PIC16F872-E/SO Datasheet - Page 100

• Manufacturer Part Number: PIC16F872-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F872
11.10.1
External interrupt on the RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
11.10.2
An overflow (FFh
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>), see Section 5.0.
EXAMPLE 11-1:
DS30221C-page 98
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
on
INT INTERRUPT
TMR0 INTERRUPT
the
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
by
00h) in the TMR0 register will set
RB0/INT
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
setting/clearing
pin,
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;(Insert user code here)
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
flag
enable
bit
INTF
bit
11.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>), see
Section 4.2.
11.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Since the upper 16 bytes of each bank are common in
PIC16F872 devices, temporary holding registers,
W_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 11-1 can be used.
PORTB INTCON CHANGE
STATUS_TEMP
© 2006 Microchip Technology Inc.
and
PCLATH_TEMP,