DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 92

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DP83816AVNG

Manufacturer Part Number
DP83816AVNG
Description
Ethernet Media Access Controller IC
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83816AVNG

Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Mounting Type
Surface Mount
Features
Physical Layer
Package / Case
144-LQFP
Package
144LQFP
Standard Supported
IEEE 802.3|IEEE 802.3u|IEEE 802.3x
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII
Data Rate
10|100 Mbps
Host Interface
PCI
Operating Supply Voltage
3.3 V
Loopback Mode
Internal
Maximum Power Dissipation
0.504 W
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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7.0 DC and AC Specifications
7.2.3 Power On Reset (PCI Active)
Note: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies.
Note: Minimum access after reset is dependent on PCI clock frequency. Accesses to DP83816 during this period will be ignored.
Note: EE is disabled for non power on reset.
7.2.4 Non Power On Reset
Note: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies.
RSTN
PCICLK
Output
RSTN
Number
Number
7.2.3.1
7.2.3.2
7.2.4.1
RSTN Active Duration from PCICLK
stable
Reset Disable to 1st PCI Cycle
EE Enabled
EE Disabled
RSTN to Output Float
Power Stable
T1
Parameter
Parameter
(Continued)
92
T1
1500
Min
Min
1
1
Reset Complete
Max
Max
40
T2
1st PCI Cycle
1st PCI Cycle
Units
Units
ms
us
us
ns
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