DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 66

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.3 Internal PHY Registers
The Internal Phy Registers are only 16 bits wide. Bits [31:16] are not used. In the following register definitions under the
‘Default’ heading, the following definitions hold true:
— RW=Read Write access
— RO=Read Only access
— LL=Latched Low and held until read, based upon the occurrence of the corresponding event
— LH=Latched High and held until read, based upon the occurrence of the corresponding event
— SC=Register sets on event occurrence and Self-Clears when event ends
— P=Register bit is Permanently set to a default value
— COR=Clear On Read
4.3.1 Basic Mode Control Register
Bit
15
14
13
12
11
10
9
8
Restart Auto-
Duplex Mode Duplex Mode: Default: dependent on the setting of the ANEG_SEL bits in the CFG register
Power Down
Negotiation
Negotiation
Bit Name
Loopback
Selection
Enable
Speed
Isolate
Reset
Auto-
Offset: 0080h
(Continued)
Tag: BMCR
Reset: Default: 0, RW/SC
1 = Initiate software Reset / Reset in Process
0 = Normal operation
This self-clearing bit returns a value of one until the reset process is complete. A reset causes all PHY
registers to return to their default values (in some cases registers defaults are defined by related bits in
the CFG register, offset 04h).
Loopback: Default: 0
1 = Loopback enabled
0 = Normal operation
The loopback function enables MII transmit data to be routed to the MII receive data path.
Setting this bit may cause the de-scrambler to lose synchronization and produce a 500 µs “dead time”
before any valid data will appear at the MII receive outputs.
Speed Select: Default: dependent on the setting of the ANEG_SEL bits in the CFG register
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100 Mb/s
0 = 10 Mb/s
Auto-Negotiation Enable: Default: dependent on the setting of the ANEG_SEL bits in the CFG register
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode.
Power Down: Default: 0
1 = Power down
0 = Normal operation
Setting this bit powers down the port.
Isolate: Default: 0
1 = Isolates the port from the MII with the exception of the serial management.
0 = Normal operation
Restart Auto-Negotiation: Default: 0, RW/SC
1 = Restart Auto-Negotiation
0 = Normal operation
When this bit is set, it re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 =
0), this bit is ignored. This bit is self-clearing and will remain a value of 1 until Auto-Negotiation is initiated,
whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management
entity clearing this bit.
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.
1 = Full Duplex operation
0 = Half Duplex operation
Access: Read Write
Size: 16 bits
66
Description
Hard Reset: XX00h
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