DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 56

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.16 Pause Control/Status Register
The PCR register is used to control and monitor the DP83816 Pause Frame reception logic. The Pause Frame reception
Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC pause interval of
the specified number of slot times.
28-24
20-17
15-0
Bit
31
30
29
23
22
21
16
PAUSE_CNT Pause Counter Value
PS_MCAST
Bit Name
PS_RCVD
MLD_EN
PS_ACT
PSNEG
PS_DA
PSEN
Offset: 0044h
(Continued)
Tag: PCR
Pause Enable
Manually enables reception of 802.3x pause frames This bit is ORed with the PSNEG bit to enable pause
reception. If pause reception has been enabled via PSEN bit (PSEN=1), setting this bit to 0 will cause
any active pause interval to be terminated. R/W
Pause on Multicast
When set to 1, this bit enables reception of 802.3x pause frames which use the 802.3x designated
multicast address in the DA (01-80-C2-00-00-01). When this mode is enabled, the RX filter logic
performs a perfect match on the above multicast address. No other address filtration modes (including
multicast hash) are required for pause frame reception. R/W
Pause on DA
When set to 1, this bit enables reception of a pause frame based on a DA match with either the perfect
match register, or one of the pattern match buffers. R/W
unused
returns 0
Pause Active
This bit is set to a 1 when the TX MAC logic is actively timing a pause interval. RO
Pause Frame Received
This bit is set to a 1 when a pause frame has been received. This bit will remain set until the TX MAC has
completed the pause interval. RO
Pause Negotiated
Status bit indicating that the 802.3x pause function has been enabled via auto-negotiation. This bit will
only be set if DP83816 advertises pause capable by setting bit 16 in the CFG register. RO
unused
returns 0
Manual Load Enable
Setting this bit to a 1 will cause the value of bits 15-0 to be written to the pause count register. This write
operation causes pause count interval to be manually initiated. This bit is not sticky, and reads will always
return 0. WO
READ: These bits represent the current real-time value of the TX MAC pause counter register.
WRITE: If no pause count interval is in progress (PS_RCVD=0, PS_ACT=0), and MLD_EN=1 this value
is written to the pause count register, and causes pause count interval to be manually initiated.
Access: Read Write
Size: 32 bits
56
Description
Hard Reset: 00000000h
Soft Reset: 00000000h
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