CS5460A-BS Cirrus Logic Inc, CS5460A-BS Datasheet - Page 49

• Manufacturer Part Number: CS5460A-BS
• Description: Driver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5460A-BS

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Driver Case Style: SSOP
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS487F4
allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.
IC
LSD
IOD
VOD
WDT
ID3:0
EOOR
EOR
VROR
IROR
PWOR
VOR
IOR
MATH
Can be deactivated only by sending a port initialization sequence to the serial port (or by exe-
cuting a software/hardware reset). When writing to the Status Register, this bit is ignored.
old (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit
cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage
threshold (PMHI), which is typically 100mV above the device’s low-voltage threshold. PMHI will
never be greater than 2.7 V.
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the current channel’s Differential Input Voltage Range.
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the current channel’s Differential Input Voltage Range.
Note:
5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy Register, then
write to the Status Register with this bit set to logic '1'. When MCLK/K is not 4.096 MHz, the
time duration is 5 * [4.096 MHz / (MCLK/K)] seconds.
ergy Accumulation Register is different than the Energy Register available through the serial
port. This register cannot be read by the user. Assertion of this bit can be caused by having
an output rate that is too small for the power being measured. The problem can be corrected
by specifying a higher frequency in the Pulse-Rate Register.
that has been accumulated during the pending computation cycle is greater than the register’s
highest allowable positive value or below the register’s lowest allowable negative value.
RMS Voltage Register.
RMS Current Register.
to fit in the Instantaneous Power Register.
too small to fit in the Instantaneous Current Register.
in the course of computation. If this bit is asserted but no other bits are asserted, then there is
no error, and this bit should be ignored.
Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command.
Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-
Modulator oscillation detect on the current channel. Set when the modulator oscillates due to
Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to
Watch-Dog Timer. Set when there has been no reading of the Energy Register for more than
Revision/Version Identification.
The internal EOUT Energy Accumulation Register went out of range. Note that the EOUT En-
Energy Out of Range. Set when the Energy Register overflows, because the amount of energy
RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the
RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the
Power Calculation Out of Range. Set when the magnitude of the calculated power is too large
Voltage Out of Range.
Current Out of Range. Set when the magnitude of the calibrated current value is too large or
General computation Indicates that a divide operation overflowed. This can happen normally
The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situation at the
inputs, when the IOD and VOD bits will re-assert themselves even after being
cleared, multiple times.
CS5460A
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