CS5460A-BS Cirrus Logic Inc, CS5460A-BS Datasheet - Page 23

• Manufacturer Part Number: CS5460A-BS
• Description: Driver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5460A-BS

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Driver Case Style: SSOP
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

sented by one pulse, the CS5460A will issue a
“burst” of one or more pulses on EOUT (and also
possibly on EDIR). The CS5460A will issue as
many pulses as are necessary to reduce the run-
ning energy accumulation value in this register to a
value that is less than the energy represented in
one pulse. If the amount of energy that has been
registered over the most recent sampling period is
large enough that it cannot be expressed with only
one pulse, then a burst of pulses will be issued,
possibly followed by a period of time during which
there will be no pulses, until the next A/D sampling
period occurs. After the pulse or pulses are issued,
a certain residual amount of energy may be left
over in this internal energy accumulation register,
which is always less (in magnitude) than the
amount of energy represented by one pulse. In this
situation, the residual energy is not lost or discard-
ed, but rather it is maintained and added to the en-
ergy that is accumulated during the next A/D
conversion cycle. The amount of residual energy
that can be left over becomes larger as the
Pulse-Rate Register is set to lower and lower val-
ues, because lower Pulse-Rate Register values
correspond to a higher amount of energy per pulse
(for a given calibration).
DS487F4
EOUT
EDIR
. . .
. . .
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)
EOUT
EDIR
t
...
...
Positive Energy Burst
Figure 11. Mechanical Counter Format on EOUT and EDIR
t
=
P u lse -R a te R e g iste r P eriod
Positive Energy
128 ms
16
=
2
x
(MCLK / K)
n
3.2.2 Mechanical Counter Format
Setting the MECH bit in the Control Register to ‘1’
and the STEP bit to ‘0’ enables wide-stepping puls-
es for mechanical counters and similar discrete
counter instruments. In this format, active-low puls-
es are 128 ms wide when using a 4.096 MHz crys-
tal and K = 1. When energy is positive, the pulses
appear on EOUT. When energy is negative, pulses
appear on EDIR. To insure that pulses will not oc-
cur at a rate faster than the 128 ms pulse duration,
or faster than the mechanical counter can accom-
modate, the Pulse-Rate Register should be set to
an appropriate value. Because the duration of
each pulse is set to 128 ms, the maximum output
pulse frequency is limited to ~7.8 Hz (for
MCLK/K = 4.096 MHz). For values of MCLK / K
different than 4.096 MHz, the duration of one pulse
is
See Figure 11 for a diagram of the typical pulse
output.
3.2.3 Stepper Motor Format
Setting the STEP bit in the Control Register to ‘1’
and the MECH bit to ‘0’ transforms the EOUT and
EDIR pins into two stepper motor phase outputs.
When enough energy has been registered by the
CS5460A to register one positive/negative energy
(128 * 4.096 MHz) / (MCLK / K) milliseconds.
fo r In te ge r n
Negative Energy
128 ms
Negative Energy Burst
...
...
CS5460A
. . .
. . .
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