LH7A404N0F000B3 NXP Semiconductors, LH7A404N0F000B3 Datasheet - Page 44

• Manufacturer Part Number: LH7A404N0F000B3
• Description: MCU ARM9, LCD CTRL, SMD, LFBGA-324
• Manufacturer: NXP Semiconductors

Specifications of LH7A404N0F000B3

• Core Size: 32bit
• No. Of I/o's: 64
• Ram Memory Size: 80KB
• Cpu Speed: 200MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LFBGA
• Supply Voltage Range: 3V
• Controller Family/series: LH7A
• Peripherals: ADC, DMA, RTC
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 80 KB
• Interface Type: EBI , IrDA , JTAG , PS2 , SCI , UART , USB
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LH7A404
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter,
2. The Bank Configuration Register (BCRx:WST1) must have Write Wait States set to a minimum of 2.
3. The number of HCLK periods that nWAIT lags assertion of nCSx must be added to the minimum value
4. No nWAIT delay cycles are added for any nWAIT assertions that occur prior to the beginning of the WSD-2 delay. These
5. Once the WSD-2 delay begins, one HCLK cycle is added to the transaction each time nWAIT is
6. Once nWAIT is sampled HIGH (de-asserted), the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, prolonged extension of
44
tIDA_nCS(x)_nWAIT
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
tA_nWAIT
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
power rail noise, and I/O condtioning will cause these timings to vary nominally. It is recommended that
designers add a small margin to avoid possible corner-case conditions.
for BCRx:WST1. For example, if nWAIT lags nCSx by 3 HCLK periods, the minimum setting of BCRx:WST1
is 2 + 3, or a total of 5 as the minimum value for BCRx:WST1.
nWAIT assertions are ignored.
sampled and queued (SQ-x). The nWAIT cycles begin being added after the Wait State Countdown reaches WSD-0.
an SMC transaction by either Wait States or nWAIT delays can cause refresh failure for the SDRAM,
and may cause SDRAM data loss.
nCS(x)
nWAIT
Transaction
HCLK
Sequence
nWE
PARAMETER
Figure 15. nWAIT Write Sequence (BCRx:WST1 = 2); Minimum Wait State Example
tDA_nCS(x)_nWAIT
WSD-2
DELAY
Delay from nCS(x) assertion to nWAIT assertion
Delay from nWAIT deassertion to nCS(x) deassertion
Delay from nWAIT deassertion to nWE deassertion
Assertion time of nWAIT
SQ-4
WSD-1
DELAY
SQ-3
WSD-0
DELAY
tA_nWAIT
SQ-2
DELAY
nWAIT
SQ-4
DESCRIPTION
NXP Semiconductors
SQ-1
DELAY
nWAIT
SQ-3
SQ-0
DELAY
nWAIT
SQ-2
tDD_nWAIT_nWE
DELAY
nWAIT
tDD_nWAIT_nCS(x)
SQ-1
DELAY
nWAIT
SQ-0
CYCLE
MIN.
END
0
2
32-Bit System-on-Chip
Preliminary data sheet
MAX.
29
4
3
HCLK periods
HCLK periods
HCLK periods
HCLK periods
UNIT
LH7A404-206
1