LH7A404N0F000B3 NXP Semiconductors, LH7A404N0F000B3 Datasheet - Page 22

• Manufacturer Part Number: LH7A404N0F000B3
• Description: MCU ARM9, LCD CTRL, SMD, LFBGA-324
• Manufacturer: NXP Semiconductors

Specifications of LH7A404N0F000B3

• Core Size: 32bit
• No. Of I/o's: 64
• Ram Memory Size: 80KB
• Cpu Speed: 200MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LFBGA
• Supply Voltage Range: 3V
• Controller Family/series: LH7A
• Peripherals: ADC, DMA, RTC
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 80 KB
• Interface Type: EBI , IrDA , JTAG , PS2 , SCI , UART , USB
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LH7A404
Vectored Interrupt Controller (VIC)
manage interrupt requests from on-chip and off-chip
sources. Each VIC performs these primary functions:
• Determine if an interrupt source is disabled or can
• Prioritize up to 16 separate interrupt sources for
• Obtain the address of the interrupt handler (vector)
• Provide a default vector and a set of status registers
to 64 different interrupts, 32 of which are vectored. The
VIC supports both FIQ and IRQ interrupts. FIQ inter-
rupts have a higher priority than IRQ interrupts. If two
interrupts with the same priority become active at the
same time, the priority must be resolved in software.
When an interrupt becomes active, the VIC generates
an FIQ or IRQ if the corresponding mask bit is set.
Interrupts are not latched in the VIC, but may latch on
a particular peripheral when applicable.
22
generate an FIQ or IRQ to the ARM core
simultaneous and nested processing
for up to 16 interrupt sources
for up to 16 non-vectored sources. Software deter-
mines the priority of these interrupts.
The LH7A404 has two VICs working together to
Two VICs are daisy-chained together to support up
SYSTEM AHB BUS
CONTROLLER
ARM922T
MMU/DMA
LCD
LCD
CONTROLLER
DMA
EMBEDDED
LCD AHB BUS
SRAM
80KB
Figure 4. External Bus Interface Block Diagram
HOST
USB
ASYNCHRONOUS
CONTROLLER
NXP Semiconductors
MEMORY
SYNCHRONOUS
CONTROLLER
(SMC)
MEMORY
(SDMC)
cleared, masking all interrupts. They must be set by
software after power-on reset to enable interrupts.
vides direct information about where its service routine
is located and eliminates software arbitration needed
with a simple interrupt controller.
modes, so external interrupts may bring the chip out of
these low power modes.
External Bus Interface
have access to an external memory system. The LCD
controller has access to an internal frame buffer in
embedded SRAM and an extension buffer in Synchro-
nous Memory for large displays. The processor and
DMA engine share the main system bus, providing
access to all external memory devices and the embed-
ded SRAM frame buffer.
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 4.
After a power-on reset, all mask register bits are
A vectored interrupt has improved latency as it pro-
The VICs continue to operate in Halt and Standby
The ARM922T, LCD controller, and DMA engine
An arbitration unit ensures that control over the
INTERFACE
EXTERNAL
INTERNAL TO
(EBI)
THE LH7A404
BUS
ADDRESS/
CONTROL
DATA
EXTERNAL TO
THE LH7A404
32-Bit System-on-Chip
Preliminary data sheet
SDRAM
SDRAM
SRAM
ROM
LH7A404-8