ADF7021BCPZ Analog Devices Inc, ADF7021BCPZ Datasheet - Page 5

• Manufacturer Part Number: ADF7021BCPZ
• Description: IC, NARROW BAND TXRX, 80-950MHZ LFCSP-48
• Manufacturer: Analog Devices Inc

Specifications of ADF7021BCPZ

• Receiving Current: 26.4mA
• Transmitting Current: 32.3mA
• Data Rate: 32.8Kbps
• Frequency Range: 80MHz To 950MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Supply Voltage Range: 2.3V To 3.6V
• Frequency: 80MHz ~ 650MHz, 862MHz ~ 940MHz
• Data Rate - Maximum: 33kbps
• Modulation Or Protocol: 2-FSK, 3-FSK, 4-FSK, MSK
• Applications: Keyless Entery, Pagers, WMTS
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -130dBm
• Voltage - Supply: 2.3 V ~ 6 V
• Current - Receiving: 20mA
• Current - Transmitting: 32.3mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7021BZ5 - BOARD DAUGHTER MATCH UNPOPULATEDEVAL-ADF7021BZ2 - BOARD DAUGHTER 860/870MHZEVAL-ADF7021BIZ - BOARD DAUGHTER 421/440MHZEVAL-ADF7021BEZ - BOARD DAUGHTER 420/440MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

SPECIFICATIONS
V
All measurements are performed with the EVAL-ADF7021DBx using the PN9 data sequence, unless otherwise noted.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter
RF CHARACTERISTICS
PHASE-LOCKED LOOP (PLL)
REFERENCE INPUT
ADC PARAMETERS
1
2
3
4
5
6
7
The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value.
VCO gain measured at a VCO tuning voltage of 1 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this
variation.
This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the PA output: −203 + 10 log(f
Guaranteed by design. Sample tested to ensure compliance.
A TCXO, VCXO, or OCXO can be used as an external oscillator.
Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
Refer to the Reference Input section for details on using an external oscillator.
DD
Frequency Ranges (Direct Output)
Frequency Ranges (RF Divide-by-2 Mode)
Phase Frequency Detector (PFD) Frequency
Phase Noise (In-Band)
Phase Noise (Out-of-Band)
Normalized In-Band Phase Noise Floor
PLL Settling
Crystal Reference
External Oscillator
Crystal Start-Up Time
Input Level for External Oscillator
INL
DNL
VCO Gain
= 2.3 V to 3.6 V, GND = 0 V, T
868 MHz, Internal Inductor VCO
434 MHz, Internal Inductor VCO
426 MHz, External Inductor VCO
160 MHz, External Inductor VCO
868 MHz, Internal Inductor VCO
433 MHz, Internal Inductor VCO
426 MHz, External Inductor VCO
XTAL Bias = 20 μA
XTAL Bias = 35 μA
OSC1
OSC2
2
4
4, 5
6
PFD
A
7
) + 20 logN.
= T
MIN
3
1
to T
Min
160
862
80
431
RF/256
3.625
3.625
MAX
, unless otherwise noted. Typical specifications are at V
Typ
58
29
27
6
−97
−103
−95
−124
−203
40
0.930
0.438
0.8
CMOS levels
±0.4
±0.4
Rev. A | Page 5 of 64
Max
650
950
325
475
26/30
26
30
Unit
MHz
MHz
MHz
MHz
MHz
MHz/V
MHz/V
MHz/V
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
μs
MHz
MHz
ms
ms
V p-p
V
LSB
LSB
Test Conditions/Comments
See Table 9 for required VCO_BIAS and
VCO_ADJUST settings
External inductor VCO
Internal inductor VCO
External inductor VCO, RF divide-by-2 enabled
Internal inductor VCO, RF divide-by-2 enabled
Crystal reference/external reference
VCO_ADJUST = 0, VCO_BIAS = 8
VCO_ADJUST = 0, VCO_BIAS = 8
VCO_ADJUST = 0, VCO_BIAS = 3
VCO_ADJUST = 0, VCO_BIAS = 2
10 kHz offset, PA = 10 dBm, V
PFD = 19.68 MHz, VCO_BIAS = 8
10 kHz offset, PA = 10 dBm, V
PFD = 19.68 MHz, VCO_BIAS = 8
10 kHz offset, PA = 10 dBm, V
PFD = 9.84 MHz, VCO_BIAS = 3
1 MHz offset, f
V
Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, loop
bandwidth (LBW) = 100 kHz
10 MHz XTAL, 33 pF load capacitors, V
10 MHz XTAL, 33 pF load capacitors, V
Clipped sine wave
V
V
DD
DD
DD
= 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8
= 2.3 V to 3.6 V, T
= 2.3 V to 3.6 V, T
RF
= 433 MHz, PA = 10 dBm,
DD
= 3 V, T
A
A
= 25°C
= 25°C
A
DD
DD
DD
= 25°C.
= 3.0 V,
= 3.0 V,
= 3.0 V,
ADF7021
DD
DD
= 3.0 V
= 3.0 V