EP7312M-CBZ Cirrus Logic Inc, EP7312M-CBZ Datasheet - Page 54
EP7312M-CBZ
Manufacturer Part Number
EP7312M-CBZ
Description
IC, 32BIT MCU, ARM7, 74MHZ, BGA-256
Manufacturer
Cirrus Logic Inc
Series
EP7r
Specifications of EP7312M-CBZ
Controller Family/series
(ARM7)
No. Of I/o's
27
Ram Memory Size
48KB
Cpu Speed
74MHz
No. Of Timers
2
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Core Size
32 Bit
Core Processor
ARM7
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Embedded Interface Type
SSI, UART
Rohs Compliant
Yes
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB7312
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1209 - KIT DEVELOPMENT EP73XX ARM7
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
598-1247
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP7312M-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
EP7312
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
54
Ball Location
*
†
‡ Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
“With p/u” means with internal pull-up of 100 KOhms on the pin.
R10
R11
R12
R13
R14
R15
R16
Strength 2 = 12 ma
T10
T11
T12
T13
T14
T15
T16
Strength 1 = 4 ma
R5
R6
R7
R8
R9
T1
T2
T3
T4
T5
T6
T7
T8
T9
PD[7]/SDQM[1]
PD[6]/SDQM[0]
A[27]/DRA[0]
A[25]/DRA[2]
A[24]/DRA[3]
A[26]/DRA[1]
VDDCORE
SSIRXFR
SSITXDA
ADCOUT
DRIVE[0]
nADCCS
VDDRTC
SSICLK
VDDIO
COL[7]
COL[3]
COL[1]
VDDIO
COL[5]
VDDIO
VSSIO
Name
D[30]
PD[3]
FB[1]
D[28]
D[25]
BUZ
Pin No.
LQFP
1
4
5
6
7
Strength
TFBGA
Ball
B3
A2
B1
E3
C1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
2
1
1
1
2
1
†
Table 22. 256-Ball PBGA Ball Listing (Continued)
Table 23. JTAG Boundary Scan Signal Ordering
Input
Input
Reset
High /
State
High
High
High
High
High
©
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
PBGA
Ball
Copyright Cirrus Logic, Inc. 2005
B1
C2
E4
D1
F5
‡
‡
(All Rights Reserved)
Core power
Pad ground
RTC power
Pad power
Pad power
Pad power
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
WRITE/nSDRAS
RUN/CLKEN
EXPCLK
Signal
nCS[5]
WORD
DAI/CODEC/SSI2 serial data output
SSI1 ADC chip select
Digital I/O power, 3.3V
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
System byte address / SDRAM address
System byte address / SDRAM address
Digital I/O power, 3.3V
System byte address / SDRAM address
Real time clock power, 2.5V
GPIO port D / SDRAM byte lane mask
GPIO port D / SDRAM byte lane mask
GPIO port D
DAI/CODEC/SSI2 serial clock
DAI/CODEC/SSI2 frame sync
Core power, 2.5V
PWM drive output
PWM feedback input
Keyboard scanner column drive
Digital I/O power, 3.3V
Buzzer drive output
Data I/O
System byte address / SDRAM address
Data I/O
I/O ground
Type
I/O
O
O
O
O
Description
Position
10
1
3
6
8
DS508F1