EP7312M-CBZ Cirrus Logic Inc, EP7312M-CBZ Datasheet - Page 14
![IC, 32BIT MCU, ARM7, 74MHZ, BGA-256](/photos/39/69/396959/bga256_sml.jpg)
EP7312M-CBZ
Manufacturer Part Number
EP7312M-CBZ
Description
IC, 32BIT MCU, ARM7, 74MHZ, BGA-256
Manufacturer
Cirrus Logic Inc
Series
EP7r
Specifications of EP7312M-CBZ
Controller Family/series
(ARM7)
No. Of I/o's
27
Ram Memory Size
48KB
Cpu Speed
74MHz
No. Of Timers
2
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Core Size
32 Bit
Core Processor
ARM7
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Embedded Interface Type
SSI, UART
Rohs Compliant
Yes
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB7312
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1209 - KIT DEVELOPMENT EP73XX ARM7
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
598-1247
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP7312M-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
EP7312
High-Performance, Low-Power System on Chip
14
CI/O
IDD
at 74 MHz
IDD
at 90 MHz
VDD
IDD
IDD
IDD
Symbol
@ 25 C
@ 70 C
@ 85 C
idle
IDLE
a.
b.
c.
STANDBY
STANDBY
STANDBY
STANDBY
Note:
Transceiver capacitance
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby supply voltage
1) Total power consumption = IDD
2) A typical design will provide 3.3 V to the I/O supply (i.e., V
2) Pull-up current = 50 µA typical at V
Refer to the strength column in the pin assignment tables for all package types.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
Parameter
1
1
1
1
1
CORE
©
DD
Min
Copyright Cirrus Logic, Inc. 2005
2.0
x 2.5 V + IDD
8
-
-
-
-
-
-
-
-
-
-
= 3.3 V.
(All Rights Reserved)
IO
Typ
77
41
10
11
6
7
x 3.3 V
-
-
-
-
-
-
DDIO
), and 2.5 V to the remaining logic. This is to allow the I/O to be
Max
1693
10.0
570
111
163
-
-
-
-
-
-
-
Unit
mA
mA
µA
µA
µA
pF
V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V
VIL = GND ± 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V
= GND ± 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V
= GND ± 0.1 V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
DD
DD
DD
Conditions
± 0.1 V,
± 0.1 V,
± 0.1 V,
DD
DD
± 0.1 V, VIL
± 0.1 V, VIL
DS508F1