EP7312M-CBZ Cirrus Logic Inc, EP7312M-CBZ Datasheet - Page 25
![IC, 32BIT MCU, ARM7, 74MHZ, BGA-256](/photos/39/69/396959/bga256_sml.jpg)
EP7312M-CBZ
Manufacturer Part Number
EP7312M-CBZ
Description
IC, 32BIT MCU, ARM7, 74MHZ, BGA-256
Manufacturer
Cirrus Logic Inc
Series
EP7r
Specifications of EP7312M-CBZ
Controller Family/series
(ARM7)
No. Of I/o's
27
Ram Memory Size
48KB
Cpu Speed
74MHz
No. Of Timers
2
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Core Size
32 Bit
Core Processor
ARM7
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Embedded Interface Type
SSI, UART
Rohs Compliant
Yes
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB7312
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1209 - KIT DEVELOPMENT EP73XX ARM7
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
598-1247
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP7312M-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Static Memory Burst Write Cycle
DS508F1
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
t
t
HWd
WDd
t
EXs
t
MWd
t
t
t
CSd
Ad
Dv
Figure 10. Static Memory Burst Write Cycle Timing Measurement
t
Dnv
©
t
EXh
Copyright Cirrus Logic, Inc. 2005
t
Ah
t
MWh
(All Rights Reserved)
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t
MWd
Dv
t
Dnv
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Ah
t
MWh
High-Performance, Low-Power System on Chip
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t
MWd
Dv
t
Dnv
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Ah
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MWh
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t
MWd
Dv
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MWh
EP7312
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CSh
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