EP7312M-CBZ Cirrus Logic Inc, EP7312M-CBZ Datasheet - Page 16
![IC, 32BIT MCU, ARM7, 74MHZ, BGA-256](/photos/39/69/396959/bga256_sml.jpg)
EP7312M-CBZ
Manufacturer Part Number
EP7312M-CBZ
Description
IC, 32BIT MCU, ARM7, 74MHZ, BGA-256
Manufacturer
Cirrus Logic Inc
Series
EP7r
Specifications of EP7312M-CBZ
Controller Family/series
(ARM7)
No. Of I/o's
27
Ram Memory Size
48KB
Cpu Speed
74MHz
No. Of Timers
2
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Core Size
32 Bit
Core Processor
ARM7
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Embedded Interface Type
SSI, UART
Rohs Compliant
Yes
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB7312
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1209 - KIT DEVELOPMENT EP73XX ARM7
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
598-1247
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP7312M-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3
the timings of each of the SDRAM modes.
16
SDCLK falling edge to SDCS assert delay time
SDCLK falling edge to SDCS deassert delay time
SDCLK falling edge to SDRAS assert delay time
SDCLK falling edge to SDRAS deassert delay time
SDCLK falling edge to SDRAS invalid delay time
SDCLK falling edge to SDCAS assert delay time
SDCLK falling edge to SDCAS deassert delay time
SDCLK falling edge to ADDR transition time
SDCLK falling edge to ADDR invalid delay time
SDCLK falling edge to SDMWE assert delay time
SDCLK falling edge to SDMWE deassert delay time
DATA transition to SDCLK falling edge time
SDCLK falling edge to DATA transition hold time
SDCLK falling edge to DATA transition delay time
through
Figure 6
define the timings associated with all phases of the SDRAM. The following table contains the values for
Parameter
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RAnv
MWa
MWd
CSa
CSd
RAa
RAd
CAa
CAd
ADv
ADx
DAs
DAh
DAd
Min
− 3
− 3
− 2
− 5
− 3
− 2
− 3
− 4
0
1
2
2
1
0
Typ
2
2
3
1
4
2
0
1
2
1
0
-
-
-
Max
10
10
15
4
7
7
5
3
5
5
5
4
-
-
DS508F1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns