AT80C51RD2-3CSUM Atmel, AT80C51RD2-3CSUM Datasheet - Page 9

• Manufacturer Part Number: AT80C51RD2-3CSUM
• Description: IC, 8BIT MCU, 80C51, 40MHZ, DIP-40
• Manufacturer: Atmel

Specifications of AT80C51RD2-3CSUM

• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Digital Ic Case Style: DIP
• Core Size: 8 Bit
• Rohs Compliant: Yes
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIL-40
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Enhanced Features
6.1
6.1.1
Figure 6-1.
4113D–8051–01/09
X2 Feature and OSC Clock Generation
Description
XTAL1
Clock Generation Diagram
F
XTAL
In comparison to the original 80C52, the microcontrollers implement the following new features:
The microcontroller core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 6-1
the XTAL1 ÷ 2 to avoid glitches when switching from X2 to standard mode.
switching mode waveforms.
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• 4-level Interrupt Priority System
• Power-off Flag
• Power On Reset
• ONCE mode
• ALE disabling
• Some enhanced features are also located in the UART and the Timer 2
• Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Saves power consumption while keeping same CPU power (oscillator power saving).
• Saves power consumption by dividing dynamically the operating frequency by 2 in operating
• Increases CPU power by 2 while keeping same crystal frequency.
and idle modes.
2
shows the clock generation block diagram. X2 bit is validated on the rising edge of
XTAL1:2
CKCON0
X2
0
1
F
OSC
8-bit Prescaler
CKRL
Idle
AT80C51RD2
Figure 6-2
CLK Periph
CLK CPU
shows the
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