AT80C51RD2-3CSUM Atmel, AT80C51RD2-3CSUM Datasheet - Page 60

• Manufacturer Part Number: AT80C51RD2-3CSUM
• Description: IC, 8BIT MCU, 80C51, 40MHZ, DIP-40
• Manufacturer: Atmel

Specifications of AT80C51RD2-3CSUM

• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Digital Ic Case Style: DIP
• Core Size: 8 Bit
• Rohs Compliant: Yes
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIL-40
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. Power-off Flag
60
AT80C51RD2
The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
applied to the device and could be generated for example by an exit from power-down.
The Power-off flag (POF) is located in PCON register (Table 16-1). POF is set by hardware
when V
ing the user to determine the type of reset.
Table 16-1.
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
CC
Number
SMOD1
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
Bit
7
7
6
5
4
3
2
1
0
PCON Register
Mnemonic Description
SMOD0
SMOD1
SMOD0
POF
GF1
GF0
IDL
Bit
PD
6
-
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when V
software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
5
-
CC
switch-on. A warm start reset occurs while V
POF
4
CC
rises from 0 to its nominal voltage. Can also be set by
GF1
3
GF0
2
PD
1
4113D–8051–01/09
CC
IDL
0
is still